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-rw-r--r--include/asm-mips/bitops.h14
-rw-r--r--include/asm-mips/byteorder.h4
-rw-r--r--include/asm-mips/interrupt.h8
3 files changed, 24 insertions, 2 deletions
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 8e802059fe67..849155aa7e8c 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -654,7 +654,12 @@ static inline unsigned long fls(unsigned long word)
{
#ifdef CONFIG_32BIT
#ifdef CONFIG_CPU_MIPS32
- __asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
+ __asm__ (
+ " .set mips32 \n"
+ " clz %0, %1 \n"
+ " .set mips0 \n"
+ : "=r" (word)
+ : "r" (word));
return 32 - word;
#else
@@ -678,7 +683,12 @@ static inline unsigned long fls(unsigned long word)
#ifdef CONFIG_64BIT
#ifdef CONFIG_CPU_MIPS64
- __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
+ __asm__ (
+ " .set mips64 \n"
+ " dclz %0, %1 \n"
+ " .set mips0 \n"
+ : "=r" (word)
+ : "r" (word));
return 64 - word;
#else
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index 584f8128fffd..4ce5bc37f403 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -19,7 +19,9 @@
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
{
__asm__(
+ " .set mips32r2 \n"
" wsbh %0, %1 \n"
+ " .set mips0 \n"
: "=r" (x)
: "r" (x));
@@ -30,8 +32,10 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
{
__asm__(
+ " .set mips32r2 \n"
" wsbh %0, %1 \n"
" rotr %0, %0, 16 \n"
+ " .set mips0 \n"
: "=r" (x)
: "r" (x));
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index 774348734fa0..50baf6bd10e7 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -20,7 +20,9 @@ __asm__ (
" .set reorder \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" ei \n"
+ " .set mips0 \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
@@ -63,7 +65,9 @@ __asm__ (
" .set push \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" di \n"
+ " .set mips0 \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
@@ -103,8 +107,10 @@ __asm__ (
" .set reorder \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" di \\result \n"
" andi \\result, 1 \n"
+ " .set mips0 \n"
#else
" mfc0 \\result, $12 \n"
" ori $1, \\result, 0x1f \n"
@@ -133,9 +139,11 @@ __asm__ (
* Slow, but doesn't suffer from a relativly unlikely race
* condition we're having since days 1.
*/
+ " .set mips32r2 \n"
" beqz \\flags, 1f \n"
" di \n"
" ei \n"
+ " .set mips0 \n"
"1: \n"
#elif defined(CONFIG_CPU_MIPSR2)
/*