diff options
| author | Leif Lindholm <leif.lindholm@linaro.org> | 2014-12-12 17:28:47 +0000 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2014-12-12 17:28:47 +0000 |
| commit | a53b88f1603cc45e6aeb9c171649a6eb8148c8df (patch) | |
| tree | 4b0b2f8d8aa806dadb2f619ec9e237ccd0397651 | |
| parent | dd1c0c0cd3c59eede221fb495dcf6846550457cc (diff) | |
| parent | fce6b7c9474b5b1b2712eb740525b1327fb4c320 (diff) | |
Merge remote-tracking branch 'rmt-1/linaro-topic-leg-acpi' into release-prep
24 files changed, 1691 insertions, 0 deletions
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000..7e59562f2 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf @@ -0,0 +1,51 @@ +## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014, ARM Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = JunoAcpiTables
+ FILE_GUID = a1dd808e-1e95-4399-abc0-653c82e8530c
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+ Facs.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl new file mode 100644 index 000000000..932e6cc00 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl @@ -0,0 +1,184 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmPlatform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
+ Scope(_SB) {
+ //
+ // A57x2-A53x4 Processor declaration
+ //
+ Device(CPU0) { // A57-0: Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) { // A57-1: Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) { // A53-0: Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) { // A53-1: Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) { // A53-2: Cluster 1, Cpu 2
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) { // A53-3: Cluster 1, Cpu 3
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+
+ //
+ // Keyboard and Mouse
+ //
+ Device(KMI0) {
+ Name(_HID, "ARMH0501")
+ Name(_CID, "PL050_KBD")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C060008, 0x4)
+ Memory32Fixed(ReadWrite, 0x1C060000, 0x4)
+ Memory32Fixed(ReadOnly, 0x1C060004, 0x4)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 }
+ })
+ }
+
+ //
+ // LAN9118 Ethernet
+ //
+ Device(ETH0) {
+ Name(_HID, "ARMH9118")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1A000000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }
+ })
+ }
+
+ // UART PL011
+ Device(COM0) {
+ Name(_HID, "ARMH0011")
+ Name(_CID, "PL011")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }
+ })
+ }
+
+ //
+ // USB Host Controller
+ //
+ Device(USB0){
+ Name(_HID, "ARMH0D20")
+ Name(_CID, "PNP0D20")
+ Name(_UID, 2)
+
+ Method(_CRS, 0x0, Serialized){
+ Name(RBUF, ResourceTemplate(){
+ Memory32Fixed(ReadWrite, 0x7FFC0000, 0x000000B0)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {149} // INT ID=149 GIC IRQ ID=117 for Juno SoC USB EHCI Controller
+ })
+ Return(RBUF)
+ }
+
+ //
+ // Root Hub
+ //
+ Device(RHUB){
+ Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
+
+ //
+ // Ports connected to Root Hub
+ //
+ Device(HUB1){
+ Name(_ADR, 0x00000001)
+ Name(_UPC, Package(){
+ 0x00, // Port is NOT connectable
+ 0xFF, // Don't care
+ 0x00000000, // Reserved 0 must be zero
+ 0x00000000 // Reserved 1 must be zero
+ })
+
+ Device(PRT1){
+ Name(_ADR, 0x00000001)
+ Name(_UPC, Package(){
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name(_PLD, Package(){
+ Buffer(0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT1
+ Device(PRT2){
+ Name(_ADR, 0x00000002)
+ Name(_UPC, Package(){
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name(_PLD, Package(){
+ Buffer(0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT2
+
+ Device(PRT3){
+ Name(_ADR, 0x00000003)
+ Name(_UPC, Package(){
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name(_PLD, Package(){
+ Buffer(0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT3
+
+ Device(PRT4){
+ Name(_ADR, 0x00000004)
+ Name(_UPC, Package(){
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name(_PLD, Package(){
+ Buffer(0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ } // USB0_RHUB_HUB1_PRT4
+ } // USB0_RHUB_HUB1
+ } // USB0_RHUB
+ } // USB0
+ } // Scope(_SB)
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Facs.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Facs.aslc new file mode 100644 index 000000000..9743ddb5e --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Facs.aslc @@ -0,0 +1,68 @@ +/** @file
+* Firmware ACPI Control Structure (FACS)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
+ 0xA152, // UINT32 HardwareSignature
+ 0, // UINT32 FirmwareWakingVector
+ 0, // UINT32 GlobalLock
+ 0, // UINT32 Flags
+ 0, // UINT64 XFirmwareWakingVector
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
+ 0, // UINT32 OspmFlags "Platform firmware must
+ // initialize this field to zero."
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Facs;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc new file mode 100644 index 000000000..ef6d786b7 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc @@ -0,0 +1,105 @@ +/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#ifdef ARM_JUNO_ACPI_5_0
+EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+#else
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+#endif
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+#if ARM_JUNO_ACPI_5_0
+ {EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3]
+#else
+ EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+#endif
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Fadt;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000..97f74820e --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc @@ -0,0 +1,109 @@ +/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)
+#define GTDT_TIMER_LEVEL_TRIGGERED (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)
+#define GTDT_TIMER_ACTIVE_LOW (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)
+#define GTDT_TIMER_ACTIVE_HIGH (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#ifdef ARM_JUNO_ACPI_5_0
+ EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags
+ };
+#else
+ #pragma pack (1)
+
+ typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT];
+ } EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+ #pragma pack ()
+
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ },
+ {
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+ }
+ };
+#endif
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Gtdt;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc new file mode 100644 index 000000000..72a35f7d8 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc @@ -0,0 +1,134 @@ +/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+//
+// Multiple APIC Description Table
+//
+#ifdef ARM_JUNO_ACPI_5_0
+ #pragma pack (1)
+
+ typedef struct {
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+ #pragma pack ()
+
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_1_0_APIC_SIGNATURE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of
+ // ACPI v5.0).
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
+ // For now we leave CPU2 (A53-0) at the first position.
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 2, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 3, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 4, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 5, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 0, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 1, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1
+ },
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
+ };
+#else
+ #pragma pack (1)
+
+ typedef struct {
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+ #pragma pack ()
+
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_1_0_APIC_SIGNATURE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+ // GsivId, GicRBase, Mpidr)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+ // ACPI v5.1).
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
+ // For now we leave CPU2 (A53-0) at the first position.
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
+ 2, 2, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
+ 3, 3, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
+ 4, 4, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
+ 5, 5, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
+ 0, 0, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
+ 1, 1, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
+ },
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
+ };
+#endif
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Madt;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc index 373d9430c..d7db5abf5 100644 --- a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc +++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc @@ -198,6 +198,13 @@ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
+
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
diff --git a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf index 66d4da79c..21f2a2dc3 100644 --- a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf +++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf @@ -105,6 +105,13 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
#
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
+
+ #
# Multiple Console IO support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
@@ -319,3 +326,9 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c index 70d632927..b123d9caa 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -15,6 +15,9 @@ #include "ArmJunoDxeInternal.h"
#include <Library/ArmShellCmdLib.h>
+// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
+STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } };
+
EFI_STATUS
EFIAPI
ArmJunoEntryPoint (
@@ -73,6 +76,12 @@ ArmJunoEntryPoint ( DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));
}
+ // Try to install the ACPI Tables
+ Status = LocateAndInstallAcpiFromFv (&mJunoAcpiTableFile);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
// Try to install the Flat Device Tree (FDT). This function actually installs the
// UEFI Driver Binding Protocol.
Status = JunoFdtInstall (ImageHandle);
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf index bf930d23d..9f8bbed76 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf @@ -32,6 +32,7 @@ MdePkg/MdePkg.dec
[LibraryClasses]
+ AcpiLib
ArmShellCmdRunAxfLib
BaseMemoryLib
BdsLib
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h index 5ebb5161f..674f42653 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h @@ -17,6 +17,7 @@ #include <Uefi.h>
+#include <Library/AcpiLib.h>
#include <Library/DebugLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h index b955dce91..badd7a64f 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h @@ -52,4 +52,32 @@ #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000
#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION 0x20140727
+#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define JUNO_WATCHDOG_COUNT 2
+
+// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
+//#define ARM_JUNO_ACPI_5_0
+
#endif
diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf new file mode 100644 index 000000000..c851d1290 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf @@ -0,0 +1,32 @@ +## +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2013, Linaro Ltd. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + apic.asl + dsdt.asl + facp.asl + gtdt.asl + +[Packages] + MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl new file mode 100644 index 000000000..f94686ee1 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [APIC] Multiple APIC Description Table (MADT) + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "APIC" +[0004] Table Length : 00000000 +[0001] Revision : 04 +[0001] Checksum : 00 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0004] Local Apic Address : 2C000000 +[0004] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000000 +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */ +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000001 +[0004] Processor UID : 00000001 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000001 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000002 +[0004] Processor UID : 00000002 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000002 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000003 +[0004] Processor UID : 00000003 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000003 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000004 +[0004] Processor UID : 00000004 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000100 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000005 +[0004] Processor UID : 00000005 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000101 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000006 +[0004] Processor UID : 00000006 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000102 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 4C +[0002] Reserved : 0000 +[0004] CPU Interface Number : 00000007 +[0004] Processor UID : 00000007 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 +[0008] Virtual GIC Base Address : 0 +[0008] Hypervisor GIC Base Address : 0 +[0004] Virtual GIC Interrupt : 0 +[0008] Redistributor Base Address : 0 +[0008] ARM MPIDR : 0000000000000103 + +[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */ +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl new file mode 100644 index 000000000..172ca3aba --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2013, Al Stone <al.stone@linaro.org> +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* +* NB: This License is also known as the "BSD 2-Clause License". +* +* +* [DSDT] Description of the armv8 VE Model +* +*/ + +DefinitionBlock ( + "dsdt.aml", // output filename + "DSDT", // table signature + 2, // DSDT compliance revision + "LINARO", // OEM ID + "RTSMVEV8", // table ID + 0x00000004) // OEM revision +{ + Scope (\_SB) + { + Method (_OSC, 4, NotSerialized) + { + /* Platform-Wide OSPM Capabilities */ + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + /* APEI support unconditionally */ + Return (Arg3) + } Else { + CreateDWordField (Arg3, Zero, CDW1) + /* Set invalid UUID error bit */ + Or (CDW1, 0x04, CDW1) + Return (Arg3) + } + } + + // + // Two Emulated aarch64 CPUs each with 4 cores + // + Device(CPU0) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CPU1) { // Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CPU2) { // Cluster 0, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CPU3) { // Cluster 0, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + Device(CPU4) { // Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CPU5) { // Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CPU6) { // Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CPU7) { // Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + + // SMC91X + Device (NET0) { + Name (_HID, "LNRO0003") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F} + }) + } + + // SYSREG + Device (SREG) { + Name (_HID, "LNRO0009") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c010000, 0x1000) + }) + Return (RBUF) + } + } + + // VIRTIO + Device (VIRT) { + Name (_HID, "LNRO0005") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c130000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A} + }) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "PL011") + Name(_UID, Zero) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1c090000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 } + }) + } + } +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl new file mode 100644 index 000000000..c288ae251 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [FACP] ACPI Table + * + */ + +[0004] Signature : "FACP" +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 18 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20111123 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 00000010 +[0001] Model : 00 +[0001] PM Profile : 04 /* Enterprise Server */ +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000001 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000001 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000001 +[0004] PM Timer Block Address : 00000001 +[0004] GPE0 Block Address : 00000001 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 01 +[0001] PM Timer Block Length : 04 +[0001] GPE0 Block Length : 08 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 1 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 1 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 1 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0001] Value to cause reset : 00 +[0002] ARM_BOOT_ARCH (decoded below) : 0001 + Use PSCI 0.2+ : 1 + PSCI Use HVC : 0 +[0001] FADT Minor Revision : 01 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000001 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 03 [DWord Access:32] +[0008] Address : 0000000000000001 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 80 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + + +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl new file mode 100644 index 000000000..d3042431c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * Hanjun Guo <hanjun.guo@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [GTDT] Generic Timer Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "GTDT" +[0004] Table Length : 00000050 +[0001] Revision : 02 +[0001] Checksum : F1 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0008] Counter Block Address : 0000000000000000 +[0004] Reserved : 00000000 + +/* In RTSM model's dts file, the last cell of interrupts + * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure EL1 Interrupt : 0000001d +[0004] SEL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Always-on : 0 + +[0004] Non-Secure EL1 Interrupt : 0000001e +[0004] NSEL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Always-on : 0 + +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Always-on : 0 + +[0004] Non-Secure EL2 Interrupt : 0000001a +[0004] NSEL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Always-on : 0 + +/* The 64-bit physical address at which the Counter Read block is located */ +[0008] CntReadBase Physical address : 0000000000000000 + +[0004] Platform Timer Count : 00000001 +[0004] Platform Timer Offset : 0000005C + +/* Memory-mapped GT (Generic Timer) structures */ +[0001] Subtable Type : 00 +[0002] Length : 0064 +[0001] Reserved : 000000 +[0008] Block Address : 000000002a810000 +[0004] Timer Count : 00000001 +[0004] Timer Offset : 00000010 + +/* One frame is available */ +[0001] Frame Number : 00 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a820000 +[0008] EL0 Base Address : FFFFFFFFFFFFFFFF +[0004] Timer Interrupt : 00000029 /* 25+16 */ +[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ + Trigger Mode : 0 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[0004] Common Flags (decoded below) : 00000000 + Secure : 0 + Always On : 0 + diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc index e6a94d475..2b16a38b6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -271,6 +271,13 @@ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf index 31a778a43..20da9c73c 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -142,6 +142,12 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+
#
# Multiple Console IO support
#
@@ -363,3 +369,8 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc index 6e5f004e2..1514eb780 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc @@ -112,6 +112,7 @@ # BDS Libraries
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
# RunAxf support via Dynamic Shell Command protocol
diff --git a/EmbeddedPkg/EmbeddedPkg.dsc b/EmbeddedPkg/EmbeddedPkg.dsc index b13693c5e..a3a136da3 100644 --- a/EmbeddedPkg/EmbeddedPkg.dsc +++ b/EmbeddedPkg/EmbeddedPkg.dsc @@ -98,6 +98,7 @@ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
# Networking Requirements
diff --git a/EmbeddedPkg/Include/Library/AcpiLib.h b/EmbeddedPkg/Include/Library/AcpiLib.h new file mode 100644 index 000000000..4d70b1cd4 --- /dev/null +++ b/EmbeddedPkg/Include/Library/AcpiLib.h @@ -0,0 +1,81 @@ +/** @file + Helper Library for ACPI + + Copyright (c) 2014, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ACPI_LIB_H__ +#define __ACPI_LIB_H__ + +#include <Uefi.h> + +// +// Macros for the Generic Address Space +// +#define NULL_GAS { EFI_ACPI_5_0_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_0_UNDEFINED, 0L } +#define ARM_GAS8(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 8, 0, EFI_ACPI_5_0_BYTE, Address } +#define ARM_GAS16(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_0_WORD, Address } +#define ARM_GAS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_DWORD, Address } +#define ARM_GASN(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_0_DWORD, Address } + +// +// Macros for the Multiple APIC Description Table (MADT) +// +#define EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector) \ + { \ + EFI_ACPI_5_0_GICD, sizeof (EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, EFI_ACPI_RESERVED_DWORD \ + } + +// Note the parking protocol is configured by UEFI if required +#define EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase) \ + { \ + EFI_ACPI_5_0_GIC, sizeof (EFI_ACPI_5_0_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuId, Flags, 0, PmuIrq, 0, GicBase \ + } + +// Note the parking protocol is configured by UEFI if required +#define EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase) \ + { \ + EFI_ACPI_5_1_GIC, sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr \ + } + +// +// SBSA Generic Watchdog +// +#define EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress, \ + ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags) \ + { \ + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \ + EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \ + WatchdogTimerGSIV, WatchdogTimerFlags \ + } + +/** + Locate and Install the ACPI tables from the Firmware Volume + + @param AcpiFile Guid of the ACPI file into the Firmware Volume + + @return EFI_SUCCESS The function completed successfully. + @return EFI_NOT_FOUND The protocol could not be located. + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateAndInstallAcpiFromFv ( + IN CONST EFI_GUID* AcpiFile + ); + +#endif // __ACPI_LIB_H__ diff --git a/EmbeddedPkg/Library/AcpiLib/AcpiLib.c b/EmbeddedPkg/Library/AcpiLib/AcpiLib.c new file mode 100644 index 000000000..cabee60cc --- /dev/null +++ b/EmbeddedPkg/Library/AcpiLib/AcpiLib.c @@ -0,0 +1,146 @@ +/** @file +* +* Copyright (c) 2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Uefi.h> + +#include <Library/AcpiLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/AcpiTable.h> +#include <Protocol/FirmwareVolume2.h> + +#include <IndustryStandard/Acpi.h> + +/** + Locate and Install the ACPI tables from the Firmware Volume + + @param AcpiFile Guid of the ACPI file into the Firmware Volume + + @return EFI_SUCCESS The function completed successfully. + @return EFI_NOT_FOUND The protocol could not be located. + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateAndInstallAcpiFromFv ( + IN CONST EFI_GUID* AcpiFile + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINT32 FvStatus; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; + INTN SectionInstance; + UINTN SectionSize; + EFI_ACPI_COMMON_HEADER *AcpiTable; + UINTN AcpiTableSize; + UINTN AcpiTableKey; + + // Ensure the ACPI Table is present + Status = gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID**)&AcpiProtocol + ); + if (EFI_ERROR (Status)) { + return Status; + } + + FvStatus = 0; + SectionInstance = 0; + + // Locate all the Firmware Volume protocols. + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Looking for FV with ACPI storage file + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID**) &FvInstance + ); + if (EFI_ERROR (Status)) { + goto FREE_HANDLE_BUFFER; + } + + while (Status == EFI_SUCCESS) { + // AcpiTable must be allocated by ReadSection (ie: AcpiTable == NULL) + AcpiTable = NULL; + + // See if it has the ACPI storage file + Status = FvInstance->ReadSection ( + FvInstance, + AcpiFile, + EFI_SECTION_RAW, + SectionInstance, + (VOID**) &AcpiTable, + &SectionSize, + &FvStatus + ); + if (!EFI_ERROR (Status)) { + AcpiTableKey = 0; + AcpiTableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) AcpiTable)->Length; + ASSERT (SectionSize >= AcpiTableSize); + + DEBUG ((EFI_D_ERROR, "- Found '%c%c%c%c' ACPI Table\n", + (((EFI_ACPI_DESCRIPTION_HEADER *) AcpiTable)->Signature & 0xFF), + ((((EFI_ACPI_DESCRIPTION_HEADER *) AcpiTable)->Signature >> 8) & 0xFF), + ((((EFI_ACPI_DESCRIPTION_HEADER *) AcpiTable)->Signature >> 16) & 0xFF), + ((((EFI_ACPI_DESCRIPTION_HEADER *) AcpiTable)->Signature >> 24) & 0xFF))); + + // Install the ACPI Table + Status = AcpiProtocol->InstallAcpiTable ( + AcpiProtocol, + AcpiTable, + AcpiTableSize, + &AcpiTableKey + ); + // Free memory allocated by ReadSection + gBS->FreePool (AcpiTable); + + if (EFI_ERROR (Status)) { + break; + } + + // Increment the section instance + SectionInstance++; + } + } + } + +FREE_HANDLE_BUFFER: + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return EFI_SUCCESS; +} diff --git a/EmbeddedPkg/Library/AcpiLib/AcpiLib.inf b/EmbeddedPkg/Library/AcpiLib/AcpiLib.inf new file mode 100644 index 000000000..cf579ded8 --- /dev/null +++ b/EmbeddedPkg/Library/AcpiLib/AcpiLib.inf @@ -0,0 +1,36 @@ +#/** @file +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiLib + FILE_GUID = 24b9d62c-5a36-417b-94b6-38dbaea90dcf + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = AcpiLib + +[Sources.common] + AcpiLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + +[Protocols] + gEfiAcpiTableProtocolGuid + gEfiFirmwareVolume2ProtocolGuid |