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17 hoursMerge remote-tracking branch 'alimon-fixes/tracking-qcomlt-fixes-alimon' ↵integration-linux-qcomltLinaro CI
into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'interconnect/tracking-qcomlt-interconnect' ↵Linaro CI
into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'cci-cams/tracking-qcomlt-cci-camss' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'db820c-fixes/db820c/5.7-rc1' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'remoteproc/tracking-qcomlt-remoteproc' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'cpuidle/wrk3/automerge/idle-branch' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'sm8250/tracking-qcomlt-sm8250' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch ↵Linaro CI
'qcs404-defconfig/tracking-qcomlt-qcs404-defconfig' into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'lt9611/tracking-qcomlt-lt9611' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch ↵Linaro CI
'sdm845-db845c-dts/tracking-qcomlt-sdm845-db845c-dts' into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'sdm845-usb/tracking-qcomlt-usb-renesas' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'bus-scaling/icc-testing' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch ↵Linaro CI
'distro.config/tracking-qcomlt-config-fragments' into integration-linux-qcomlt
17 hoursMerge remote-tracking branch ↵Linaro CI
'arm64-defconfig/tracking-qcomlt-arm64-defconfig' into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'iommu/tracking-qcomlt-iommu' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'drm-msm/tracking-qcomlt-drm-msm' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch ↵Linaro CI
'fixes/tracking-qcomlt-fixes-without-devfreq-reverts' into integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'audio/tracking-qcomlt-audio' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'wcd9335/tracking-qcomlt-wcd9335' into ↵Linaro CI
integration-linux-qcomlt
17 hoursMerge remote-tracking branch 'msm8996-dt/tracking-qcomlt-msm8996-dt' into ↵Linaro CI
integration-linux-qcomlt
17 hoursarm64: dts: qcom: sm8250: pin MMCX to stop the board from crashingtracking-qcomlt-sm8250Dmitry Baryshkov
To prevent random crashes/reboots, pin MMCX domain to dispcc node till the cause is found. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursarm64: dts: sm8250: add DSI and MDP OPP tables and power-domainsDmitry Baryshkov
Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursdrm/msm/dpu: dev_pm_opp_put_clkname() only when an opp_table existsRajendra Nayak
Its possible that dpu_bind() fails early enough before dev_pm_opp_set_clkname() is called. In such cases, unconditionally calling dev_pm_opp_put_clkname() in dpu_unbind() can result in a crash. Put an additional check so that dev_pm_opp_put_clkname() is called only when an opp_table exists. Fixes: aa3950767d05 ("drm/msm/dpu: Use OPP API to set clk/perf state") Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
17 hoursopp: Fix dev_pm_opp_set_rate() to not return earlyRajendra Nayak
dev_pm_opp_set_rate() can now be called with freq = 0 inorder to either drop performance or bandwidth votes or to disable regulators on platforms which support them. In such cases, a subsequent call to dev_pm_opp_set_rate() with the same frequency ends up returning early because 'old_freq == freq' Instead make it fall through and put back the dropped performance and bandwidth votes and/or enable back the regulators. Fixes: cd7ea582 ("opp: Make dev_pm_opp_set_rate() handle freq = 0 to drop performance votes") Reported-by: Sajida Bhanu <sbhanu@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
17 hoursdrm/msm: dsi: dev_pm_opp_put_clkname() only when an opp_table existsRajendra Nayak
Its possible for msm_dsi_host_init() to fail early, before dev_pm_opp_set_clkname() is called. In such cases, unconditionally calling dev_pm_opp_put_clkname() in msm_dsi_host_destroy() results in a crash. Put an additional check so that dev_pm_opp_put_clkname() is called only when an opp_table exists. Fixes: f99131fa7a23 ("drm/msm: dsi: Use OPP API to set clk/perf state") Reported-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
17 hoursdrm/msm: dsi: Use OPP API to set clk/perf stateRajendra Nayak
On SDM845 and SC7180 DSI needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate() for devices without an OPP table, hence the change works fine on devices/platforms which only need to set a clock rate. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
17 hoursdrm/msm/dpu: Use OPP API to set clk/perf stateRajendra Nayak
On some qualcomm platforms DPU needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
17 hoursdrm: msm: dsi_pll_7nm fixesDmitry Baryshkov
Apply several fixes from the downstream tree. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursdrm/msm/dpu: request for display color blocks based on hw catalog entryKalyan Thota
Request for color processing blocks only if they are available in the display hw catalog and they are sufficient in number for the selection. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Fixes: e47616df008b ("drm/msm/dpu: add support for color processing Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
17 hoursdrm/msm/dsi: attach external bridge with DRM_BRIDGE_ATTACH_NO_CONNECTORVinod Koul
Modern bridges do not create the connector and expect the display driver to do so. Hence, create the drm connector in msm display driver and add use flag DRM_BRIDGE_ATTACH_NO_CONNECTOR to attach bridges Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
17 hoursWIP: drm: bridge: add support for lontium LT9611UXC bridgeDmitry Baryshkov
Add support for Lontium LT9611UXC HDMI bridge. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursarm64: qcom: sm8250: add mdss interconnect nodesDmitry Baryshkov
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursarm64: dts: qcom: sm8250: add interconnect nodesJonathan Marek
Add the interconnect dts nodes for sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
17 hoursarm64: dts: qcom: sm8150: add interconnect nodesJonathan Marek
Add the interconnect dts nodes for sm8150. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
17 hoursinterconnect: qcom: Add SM8250 interconnect provider driverJonathan Marek
Add driver for the Qualcomm interconnect buses found in SM8250 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Based on SC7180 driver and generated from downstream dts. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
17 hoursinterconnect: qcom: Add SM8150 interconnect provider driverJonathan Marek
Add driver for the Qualcomm interconnect buses found in SM8150 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Based on SC7180 driver and generated from downstream dts. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
17 hoursdt-bindings: interconnect: Add Qualcomm SM8250 DT bindingsJonathan Marek
The Qualcomm SM8250 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org>
17 hoursdt-bindings: interconnect: Add Qualcomm SM8150 DT bindingsJonathan Marek
The Qualcomm SM8150 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org>
17 hoursdt-bindings: interconnect: single yaml file for RPMh interconnect driversJonathan Marek
These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 interconnect bindings. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
17 hoursarm64: dts: qcom: rb5: Enable PCIe ports and PHYManivannan Sadhasivam
RB5 has 3 PCIe ports exposed to connect PCIe client devices. PCIe0 is connected to QCA6391 chipset and others are available on the HS3 expansion connector. Hence, enable all of them. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
17 hoursregulator: qcom-rpmh: Increase voltage setpoints for PM8009 SMPS2Manivannan Sadhasivam
The PM8009 SMPS2 regulator is capable of supporting more voltage ranges. Hence, modify its hw_data to reflect the same. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
17 hourspci: controller: dwc: qcom: Add PCIe support for SM8250 SoCManivannan Sadhasivam
The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the 2.7.0 ops. Only difference is the need of ATU base, which will be fetched opionally if provided by DT/ACPI. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
29 hoursarm64: dts: qcom: sm8250: Add PCIe suppportManivannan Sadhasivam
Add PCIe support for Qcom SM8250 SoC. This SoC has 3 PCIe Gen 3 instances based on Designware IP, out of which PCIe0 has 1 lane support and the rest have 2 lane support. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
31 hoursdt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoCManivannan Sadhasivam
Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
31 hoursphy: qualcomm: phy-qcom-qmp: Add PCIe PHY support for SM8250 SoCManivannan Sadhasivam
SM8250 has two different PHY versions: QMP PHY - 1 lane QHP PHY - 2 lanes Add support for these with relevant init sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
31 hoursdt-bindings: phy: qcom,qmp: Document SM8250 PCIe PHY bindingsManivannan Sadhasivam
Document the SM8250 PCIe PHY DT bindings. The PHY IPs (QMP, QHP) are similar to the ones used on SDM845 hence just add the compatibles Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
31 hoursarch64: dts: qcom: sm8250: add uart nodesDmitry Baryshkov
Currently sm8250.dtsi only defines default debug uart. Port rest uart nodes from the downstream dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
31 hoursarm64: dts: qcom: sm8250: include xo clock to sdhc clocks listDmitry Baryshkov
Include xo clock to sdhc clocks list which will be used in calculating MCLK_FREQ field of DLL_CONFIG2 register. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
31 hoursarm64: dts: qrb5165-rb5: port thermal zone definitionsDmitry Baryshkov
Add thermal zones definitions basing on the downstream kernel. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
31 hoursarm64: dts: qcom: sm8250-mtp: add display nodesDmitry Baryshkov
Add mdss, mdp, dsi0/dsi0_phy (with absent panel configuration) and disabled dsi1/dsi1_phy nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>