mmc: dw_mmc-hisilicon: auto choose parent

Revert the workaround of setting register 1b73b098fd39403882ff20061c707e420a95e885
Clock parent can be auto choose

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

2 files changed, 39 insertions, 34 deletions

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index d138d2fb8ca3..fb95b9361911 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -78,12 +78,6 @@
 		clock-frequency = <1300000000>;
 		clock-output-names = "armpll5";
 	};
-	test_sd_clk: clk@7 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-		clock-output-names = "testsdclk";
-	};
 
 	amba {
 		#address-cells = <1>;
@@ -308,6 +302,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_mmc1";
 				hisilicon,clkmux-reg = <0x108 0x200>;
 				hisilicon,clkmux-table = <0 0x200>;
 			};
@@ -315,6 +310,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_mmc2";
 				hisilicon,clkmux-reg = <0x140 0x10>;
 				hisilicon,clkmux-table = <0 0x10>;
 			};
@@ -322,6 +318,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_mmc3";
 				hisilicon,clkmux-reg = <0x140 0x200>;
 				hisilicon,clkmux-table = <0 0x200>;
 			};
@@ -329,6 +326,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_sd";
 				hisilicon,clkmux-reg = <0x108 0x10>;
 				hisilicon,clkmux-table = <0 0x10>;
 			};
@@ -336,6 +334,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&osc26m &div_mmc1>;
+				clock-output-names = "rclk_mmc1_parent";
 				hisilicon,clkmux-reg = <0x108 0x400>;
 				hisilicon,clkmux-table = <0 0x400>;
 			};
@@ -343,6 +342,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_venc";
 				hisilicon,clkmux-reg = <0x10c 0x800>;
 				hisilicon,clkmux-table = <0 0x800>;
 			};
@@ -350,6 +350,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_g2d";
 				hisilicon,clkmux-reg = <0x10c 0x20>;
 				hisilicon,clkmux-table = <0 0x20>;
 			};
@@ -357,6 +358,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_vdec";
 				hisilicon,clkmux-reg = <0x110 0x20>;
 				hisilicon,clkmux-table = <0 0x20>;
 			};
@@ -364,6 +366,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb>;
+				clock-output-names = "rclk_vpp";
 				hisilicon,clkmux-reg = <0x110 0x800>;
 				hisilicon,clkmux-table = <0 0x800>;
 			};
@@ -371,6 +374,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb &pll_hdmi>;
+				clock-output-names = "rclk_ldi0";
 				hisilicon,clkmux-reg = <0x114 0x6000>;
 				hisilicon,clkmux-table = <0 0x6000>;
 			};
@@ -378,6 +382,7 @@
 				compatible = "hisilicon,hi3620-clk-mux";
 				#clock-cells = <0>;
 				clocks = <&pll_peri &pll_usb &pll_hdmi>;
+				clock-output-names = "rclk_ldi1";
 				hisilicon,clkmux-reg = <0x118 0xc000>;
 				hisilicon,clkmux-table = <0 0xc000>;
 			};
@@ -863,7 +868,7 @@
 			mmcclk1: clkgate@56 {
 				compatible = "hisilicon,hi3620-clk-gate";
 				#clock-cells = <0>;
-				clocks = <&test_sd_clk>;
+				clocks = <&refclk_mmc1_parent>;
 				clock-output-names = "clk_mmc1";
 				hisilicon,hi3620-clkgate = <0x50 0x200000>;
 			};
@@ -884,7 +889,7 @@
 			sdclk: clkgate@59 {
 				compatible = "hisilicon,hi3620-clk-gate";
 				#clock-cells = <0>;
-				clocks = <&test_sd_clk>;
+				clocks = <&div_sd>;
 				clock-output-names = "clk_sd";
 				hisilicon,hi3620-clkgate = <0x50 0x100000>;
 			};
@@ -977,6 +982,7 @@
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc1>;
+				clock-output-names = "div_mmc1";
 				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x108 0x1e0>;
 			};
@@ -984,6 +990,7 @@
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc2>;
+				clock-output-names = "div_mmc2";
 				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x140 0xf>;
 			};
@@ -991,6 +998,7 @@
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc3>;
+				clock-output-names = "div_mmc3";
 				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x140 0x1e0>;
 			};
@@ -998,6 +1006,7 @@
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_sd>;
+				clock-output-names = "div_sd";
 				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x108 0xf>;
 			};
diff --git a/drivers/mmc/host/dw_mmc-hisilicon.c b/drivers/mmc/host/dw_mmc-hisilicon.c
index 5ca1d267cdce..f1add977f009 100644
--- a/drivers/mmc/host/dw_mmc-hisilicon.c
+++ b/drivers/mmc/host/dw_mmc-hisilicon.c
@@ -186,31 +186,20 @@ static void dw_mci_hs_set_timing(int idx, int sam, int drv, int div)
 	spin_unlock_irqrestore(&mmc_tuning_lock, flags);
 }
 
-extern void __iomem *hs_sctrl_base;
 static void dw_mci_hs_tun(struct dw_mci *host, int id, int index)
 {
-	int input_clk = hs_tuning_config[id][index][0];
-	int rate = 0;
+	struct dw_mci_hs_priv_data *priv = host->priv;
+	int ret;
 
 	if (!pctrl)
 		return;
 
-	if (id == 0) {
-		rate = 1440000000/input_clk - 1;
-		/* sd choose pll2 */
-		writel(0x1f<<16 | rate, hs_sctrl_base + 0x108);
-	} else if (id == 1) {
-		if (input_clk == 26000000) {
-			rate = 26000000/input_clk - 1;
-			writel(((0x7E0<<16) | (0x0<<9) | (rate<<5)),
-						hs_sctrl_base + 0x108);
-		} else {
-			rate = 1440000000/input_clk - 1;
-			/* emmc choose pll2 */
-			writel(((0x7E0<<16) | (0x2<<9) | (rate<<5)),
-						hs_sctrl_base + 0x108);
-		}
-	}
+	if (priv->old_timing == index)
+		return;
+
+	ret = clk_set_rate(host->ciu_clk, hs_tuning_config[id][index][0]);
+	if (ret)
+		dev_err(host->dev, "clk_set_rate failed\n");
 
 	dw_mci_hs_set_timing(id,
 			(hs_tuning_config[id][index][3] +
@@ -219,6 +208,7 @@ static void dw_mci_hs_tun(struct dw_mci *host, int id, int index)
 			hs_tuning_config[id][index][1]);
 
 	host->bus_hz = hs_tuning_config[id][index][5];
+	priv->old_timing = index;
 }
 
 static void dw_mci_hs_set_ios(struct dw_mci *host, struct mmc_ios *ios)
@@ -226,12 +216,8 @@ static void dw_mci_hs_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 	struct dw_mci_hs_priv_data *priv = host->priv;
 	int id = priv->id;
 
-	if ((priv->old_timing != ios->timing)) {
-		if (priv->type == DW_MCI_TYPE_HI4511)
-			dw_mci_hs_tun(host, id, ios->timing);
-
-		priv->old_timing = ios->timing;
-	}
+	if (priv->type == DW_MCI_TYPE_HI4511)
+		dw_mci_hs_tun(host, id, ios->timing);
 }
 
 static int dw_mci_hs_priv_init(struct dw_mci *host)
@@ -262,13 +248,22 @@ static int dw_mci_hs_priv_init(struct dw_mci *host)
 						"hisilicon,pctrl");
 			pctrl = of_iomap(node, 0);
 		}
+	}
 
+	return 0;
+}
+
+static int dw_mci_hs_setup_clock(struct dw_mci *host)
+{
+	struct dw_mci_hs_priv_data *priv = host->priv;
+
+	if (priv->type == DW_MCI_TYPE_HI4511)
 		dw_mci_hs_tun(host, priv->id, 0);
-	}
 
 	return 0;
 }
 
+
 static irqreturn_t dw_mci_hs_card_detect(int irq, void *data)
 {
 	struct dw_mci *host = (struct dw_mci *)data;
@@ -331,6 +326,7 @@ static const struct dw_mci_drv_data hs_drv_data = {
 	.init			= dw_mci_hs_priv_init,
 	.setup_bus		= dw_mci_hs_setup_bus,
 	.set_ios		= dw_mci_hs_set_ios,
+	.setup_clock		= dw_mci_hs_setup_clock,
 };
 
 static const struct of_device_id dw_mci_hs_match[] = {