PM: debug: using cpu_suspend; checking sctrl+0xFC

2 files changed, 79 insertions, 45 deletions

diff --git a/arch/arm/mach-hs/hilpm-cpugodp.S b/arch/arm/mach-hs/hilpm-cpugodp.S
index c984a2ee7687..d06b7eb80c88 100644
--- a/arch/arm/mach-hs/hilpm-cpugodp.S
+++ b/arch/arm/mach-hs/hilpm-cpugodp.S
@@ -446,7 +446,7 @@ xmmu_enalbed:
 	mcr	p15, 0, r5, c3, c0, 0	@ domain access control reg
 
 return_to_c:
-	mov 	r0, r10
+	mov 	r0, r10		@ mark (r10) is returned to C
 	LDMFD   sp!, {r4-r11, pc}   /* succeed */
 
 @========
@@ -1181,6 +1181,16 @@ SecuramBegin:
 xx
 	instr_sync
 	nop
+	LDR  r4,=REG_BASE_SCTRL
+	LDR    r4,=REG_BASE_PMCTRL
+	LDR	r1, =REG_BASE_PCTRL
+	LDR	r1, =REG_BASE_PMUSPI
+	LDR   r2,=0x01000007  @BIT24: Enable DpSleep Mode, BIT2|BIT1|BIT0 = 7
+	LDR   r4,=REG_BASE_L2CC
+	LDR   r4,=REG_BASE_A9PER
+	LDR   r1,=0x03030303  @all CPU to Power-off Mode
+	LDR r4,=SECURAM_CODE_READY_FLAG
+
 	mov 	r10, #0x90	@ mark
 	mov 	pc, r6 		@ go to xcpu_resume
 
@@ -1308,6 +1318,10 @@ r_wait_ddrcclk_ok:
 	@LDR   r1,[r4,#0xc]
 	@TST   r1,#0x01
 	@BNE   Back_from_WFI  @go directly to  Resume
+/* debug */
+	LDR   r1,[r4,#0xc]
+	TST   r1,#0x01
+dd_err:	BNE   dd_err  @ go directly to  Resume
 
 	/* exit intr response mode */
 	LDR r2,[r4,#8]
@@ -1376,6 +1390,10 @@ r_wait_ddrcclk_ok:
 	 **/
 	DSB
 /* TODO: debug */
+	/* to check SCCPUCORESTAT */
+	LDR     R4, =REG_BASE_SCTRL
+	LDR     R10, [R4, #0xFC]
+
 	NOP
 	WFI
 /* debug */
@@ -1386,8 +1404,8 @@ xldo3delay:
 	BNE	xldo3delay
 
 /* debug */
-	MOV 	r10,  pc	@ mark
-
+/*	MOV 	r10,  pc	@ mark
+ */
 	NOP
 	NOP
 	NOP
diff --git a/arch/arm/mach-hs/pm.c b/arch/arm/mach-hs/pm.c
index 6e84a1cf2afb..9b81dee1a4ac 100644
--- a/arch/arm/mach-hs/pm.c
+++ b/arch/arm/mach-hs/pm.c
@@ -46,6 +46,7 @@
 #include <linux/of_device.h>
 #include <linux/of_address.h>
 #include <linux/of_gpio.h>
+#include <linux/cpu_pm.h>
 #include "core.h"
 #include "hipm.h"
 
@@ -56,6 +57,7 @@ extern struct cpu_num_limit gcpu_num_limit;
 extern void pmulowpower(int isuspend);
 extern unsigned long hi_cpu_godpsleep_ddrbase;
 extern unsigned long hi_cpu_godpsleep_phybase;
+extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
 
 /* CPU0 use timer0 as input clk, before enter suspend status
@@ -623,10 +625,49 @@ static void hisik3_power_off(void)
 	gpio_free(pmu_power_off_handle);
 }
 
+static int wrapper_hs_godpsleep(unsigned long t)
+{
+#define REG_BK_LEN 	(0x30)
+	void __iomem *tmp_addr = NULL; /* debug */
+	int i;
+	u32 reg_backup[REG_BK_LEN];
+	u32 *tarray;
+
+#if 0
+	int j;
+/* debug, to dump TTBR0 translation table */
+	tarray = get_ttbr0();
+	tarray = hisi_p2v(tarray);
+	printk("TTBR0 Translation Table Dump:\n");
+	for(i = 0; i < 0x400; i++) {
+		printk("0x%04x: ", i*4*4); /* as byte */
+		for(j = 0; j < 0x04; j++)
+			printk("0x%08x ", tarray[i*4+j]);
+		printk("\n");
+	}
+#endif
+	for(i = 0; i < REG_BK_LEN; i++)
+		reg_backup[i] = 0;
+
+	tmp_addr = hilpm_cpu_godpsleep(reg_backup);
+
+	for(i = 0; i < REG_BK_LEN; i++)
+		printk("reg_backup[0x%02x] = 0x%08x\n", i, reg_backup[i]);
+	/* dump hi_cpu_godpsleep_ddrbase */
+	tarray = (u32*) hi_cpu_godpsleep_ddrbase;
+	for(i = 0; i < 0x10; i++)
+		printk("hi_cpu_godpsleep_ddrbase[0x%02x] = 0x%08x\n", i,
+								tarray[i]);
+	/* TODO: debug */
+	printk("hilpm_cpu_godpsleep return val: 0x%x\n",
+		(u32)tmp_addr);
+
+	return 0;
+}
+
 static int hisik3_pm_enter(suspend_state_t state)
 {
 	unsigned long flage = 0;
-	void __iomem *tmp_addr = NULL; /* debug */
 
 	/* debug */
 	pr_emerg("Enter %s\n", __func__);
@@ -647,6 +688,12 @@ static int hisik3_pm_enter(suspend_state_t state)
 	}
 #endif
 	local_irq_save(flage);
+
+	cpu_pm_enter();
+	printk("after cpu_pm_enter\n");
+	cpu_cluster_pm_enter();
+	printk("after cpu_cluster_pm_enter\n");
+
 #ifdef CONFIG_CACHE_L2X0
 	outer_flush_all();
 	outer_disable();
@@ -683,13 +730,14 @@ static int hisik3_pm_enter(suspend_state_t state)
 #ifdef CONFIG_LOWPM_DEBUG
 	/*time enable*/
 	timer0_0_enable();
-
+xx
 	/*rtc*/
 	rtc_enable();
 #endif
 
 	/* debug: time enable*/
-	timer0_0_enable();
+/*	timer0_0_enable();
+ */
 
 	/* TODO: debug */
 //	printk("Call flush_cache_all()\n");
@@ -700,49 +748,13 @@ static int hisik3_pm_enter(suspend_state_t state)
 	printk("before hilpm_cpu_godpsleep\n");
 
 /* TODO: should call hilpm here */
-{
-#define REG_BK_LEN 	(0x30)
-	int i;
-	u32 reg_backup[REG_BK_LEN];
-	u32 *tarray;
-
-#if 0
-	int j;
-/* debug, to dump TTBR0 translation table */
-	tarray = get_ttbr0();
-	tarray = hisi_p2v(tarray);
-	printk("TTBR0 Translation Table Dump:\n");
-	for(i = 0; i < 0x400; i++) {
-		printk("0x%04x: ", i*4*4); /* as byte */
-		for(j = 0; j < 0x04; j++)
-			printk("0x%08x ", tarray[i*4+j]);
-		printk("\n");
-	}
-#endif
-	for(i = 0; i < REG_BK_LEN; i++)
-		reg_backup[i] = 0;
-
-	tmp_addr = hilpm_cpu_godpsleep(reg_backup);
-
-	for(i = 0; i < REG_BK_LEN; i++)
-		printk("reg_backup[0x%02x] = 0x%08x\n", i, reg_backup[i]);
-	/* dump hi_cpu_godpsleep_ddrbase */
-	tarray = (u32*) hi_cpu_godpsleep_ddrbase;
-	for(i = 0; i < 0x10; i++)
-		printk("hi_cpu_godpsleep_ddrbase[0x%02x] = 0x%08x\n", i,
-								tarray[i]);
-
-}
-	/* TODO: debug */
-	printk("VA of A9_PRE_STORE_DATA_ADDR calc'ed by assembly is: 0x%x\n",
-		(u32)tmp_addr);
-
+	cpu_suspend(0, wrapper_hs_godpsleep);
 
 	printk("after hilpm_cpu_godpsleep\n");
 
 	/* debug: disable timer0*/
-	timer0_0_disable();
-
+/*	timer0_0_disable();
+ */
 #ifdef K3_EDB_TMP
 	/*uart init.*/
 	edb_reinit();
@@ -765,6 +777,10 @@ static int hisik3_pm_enter(suspend_state_t state)
 #ifdef CONFIG_CACHE_L2X0
 	outer_resume();
 #endif
+	cpu_cluster_pm_exit();
+	cpu_pm_exit();
+	printk("after cpu_pm_exit()\n");
+
 	/* restore timer0_0 timer0_1 and enable timer0 clk */
 	restore_timer0_register();