Platform/Marvell: ComPhyLib: Enable SATA PHY init for multiple devices

Add support for multiple SATA host controllers to SERDES library.
Remove single SATA controller base address from the description
files and use shared platform description structure. This allows to
reduce redundancy and pick existing PCD, used by PciEmulation.

Move and rename DEV_ENABLED macro from PciEmulation driver, so that
it can be reused in other places, where description templates are used.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

6 files changed, 40 insertions, 25 deletions

diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc
index ab8fa3d..126d324 100644
--- a/Platforms/Marvell/Armada/Armada70x0.dsc
+++ b/Platforms/Marvell/Armada/Armada70x0.dsc
@@ -147,6 +147,3 @@
   #ResetLib

   gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084

   gMarvellTokenSpaceGuid.PcdResetRegMask|0x1

-

-  #SATA

-  gMarvellTokenSpaceGuid.PcdSataBaseAddress|0xF2540000

diff --git a/Platforms/Marvell/Include/Library/MvHwDescLib.h b/Platforms/Marvell/Include/Library/MvHwDescLib.h
index 47bc4ce..73e629d 100644
--- a/Platforms/Marvell/Include/Library/MvHwDescLib.h
+++ b/Platforms/Marvell/Include/Library/MvHwDescLib.h
@@ -38,6 +38,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include <Library/NonDiscoverableDeviceRegistrationLib.h>

 

 //

+// Helper macros

+//

+

+// Check if device is enabled - it expects PCD to be read to '<type>DeviceTable' array

+#define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index])

+

+//

 // NonDiscoverable devices description template definition

 //

 #define MVHW_MAX_XHCI_DEVS         4

@@ -71,7 +78,9 @@ typedef struct {
 #define MVHW_CP1_XHCI1_BASE        0xF4510000

 

 #define MVHW_CP0_AHCI0_BASE        0xF2540000

+#define MVHW_CP0_AHCI0_ID          0

 #define MVHW_CP1_AHCI0_BASE        0xF4540000

+#define MVHW_CP1_AHCI0_ID          1

 

 #define MVHW_AP0_SDHCI0_BASE       0xF06E0000

 #define MVHW_CP0_SDHCI0_BASE       0xF2780000

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 3987183..c71ddb6 100755
--- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -33,6 +33,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/

 

 #include "ComPhyLib.h"

+#include <Library/MvHwDescLib.h>

 

 #define SD_LANE_ADDR_WIDTH          0x1000

 #define HPIPE_ADDR_OFFSET           0x800

@@ -41,6 +42,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define HPIPE_ADDR(base, Lane)      (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)

 #define COMPHY_ADDR(base, Lane)     (base + COMPHY_ADDR_LANE_WIDTH * Lane)

 

+DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;

+

 /*

  * For CP-110 we have 2 Selector registers "PHY Selectors"

  * and " PIPE Selectors".

@@ -702,24 +705,34 @@ UINTN
 ComPhySataPowerUp (

   IN UINT32 Lane,

   IN EFI_PHYSICAL_ADDRESS HpipeBase,

-  IN EFI_PHYSICAL_ADDRESS ComPhyBase

+  IN EFI_PHYSICAL_ADDRESS ComPhyBase,

+  IN UINT8 SataHostId

   )

 {

   EFI_STATUS Status;

+  UINT8 *SataDeviceTable;

+  MVHW_NONDISCOVERABLE_DESC *Desc = &mA7k8kNonDiscoverableDescTemplate;

   EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);

   EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);

   EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);

-  EFI_PHYSICAL_ADDRESS SataBase;

 

-  SataBase = PcdGet32 (PcdSataBaseAddress);

-  if (SataBase == 0) {

-    DEBUG((DEBUG_INFO, "ComPhy: SATA address not defined\n"));

-    return EFI_D_ERROR;

+  SataDeviceTable = (UINT8 *) PcdGetPtr (PcdPciEAhci);

+

+  if (SataDeviceTable == NULL || SataHostId >= PcdGetSize (PcdPciEAhci)) {

+    DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHostId));

+    return EFI_INVALID_PARAMETER;

+  }

+

+  if (!MVHW_DEV_ENABLED (Sata, SataHostId)) {

+    DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHostId));

+    return EFI_INVALID_PARAMETER;

   }

 

+  DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n"));

+

   DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power down ComPhy\n"));

 

-  ComPhySataMacPowerDown (SataBase);

+  ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]);

 

   DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));

 

@@ -735,7 +748,7 @@ ComPhySataPowerUp (
 

   DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));

 

-  ComPhySataPhyPowerUp (SataBase);

+  ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]);

 

   DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));

 

@@ -1018,9 +1031,11 @@ ComPhyCp110Init (
       break;

     case PHY_TYPE_SATA0:

     case PHY_TYPE_SATA1:

+      Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP0_AHCI0_ID);

+      break;

     case PHY_TYPE_SATA2:

     case PHY_TYPE_SATA3:

-      Status = ComPhySataPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);

+      Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP1_AHCI0_ID);

       break;

     case PHY_TYPE_USB3_HOST0:

     case PHY_TYPE_USB3_HOST1:

@@ -1040,8 +1055,8 @@ ComPhyCp110Init (
       ASSERT (FALSE);

       break;

     }

-    if (EFI_ERROR(Status))

-      DEBUG((DEBUG_ERROR, "PLL is not locked - Failed to initialize Lane %d\n",

-        Lane));

+    if (EFI_ERROR(Status)) {

+      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));

+    }

   }

 }

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
index a7ee1f8..02905a5 100644
--- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -105,5 +105,4 @@
   gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds

   gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags

 

-  #SATA

-  gMarvellTokenSpaceGuid.PcdSataBaseAddress

+  gMarvellTokenSpaceGuid.PcdPciEAhci

diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec
index 313eaa6..4be9a22 100644
--- a/Platforms/Marvell/Marvell.dec
+++ b/Platforms/Marvell/Marvell.dec
@@ -176,9 +176,6 @@
   gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176

   gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177

 

-#SATA

-  gMarvellTokenSpaceGuid.PcdSataBaseAddress|0|UINT32|0x4000052

-

 #UtmiPhy

   gMarvellTokenSpaceGuid.PcdUtmiPhyCount|0|UINT32|0x30000205

   gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|{ 0x0 }|VOID*|0x30000206

diff --git a/Platforms/Marvell/PciEmulation/PciEmulation.c b/Platforms/Marvell/PciEmulation/PciEmulation.c
index 213ac32..35f1a87 100644
--- a/Platforms/Marvell/PciEmulation/PciEmulation.c
+++ b/Platforms/Marvell/PciEmulation/PciEmulation.c
@@ -50,8 +50,6 @@ STATIC UINT8 * CONST XhciDeviceTable = FixedPcdGetPtr (PcdPciEXhci);
 STATIC UINT8 * CONST AhciDeviceTable = FixedPcdGetPtr (PcdPciEAhci);

 STATIC UINT8 * CONST SdhciDeviceTable = FixedPcdGetPtr (PcdPciESdhci);

 

-#define DEV_ENABLED(type, index) (type ## DeviceTable[index])

-

 //

 // NonDiscoverable devices registration

 //

@@ -70,7 +68,7 @@ PciEmulationInitXhci (
   }

 

   for (i = 0; i < Desc->XhciDevCount; i++) {

-    if (!DEV_ENABLED(Xhci, i)) {

+    if (!MVHW_DEV_ENABLED (Xhci, i)) {

       continue;

     }

 

@@ -107,7 +105,7 @@ PciEmulationInitAhci (
   }

 

   for (i = 0; i < Desc->AhciDevCount; i++) {

-    if (!DEV_ENABLED(Ahci, i)) {

+    if (!MVHW_DEV_ENABLED (Ahci, i)) {

       continue;

     }

 

@@ -144,7 +142,7 @@ PciEmulationInitSdhci (
   }

 

   for (i = 0; i < Desc->SdhciDevCount; i++) {

-    if (!DEV_ENABLED(Sdhci, i)) {

+    if (!MVHW_DEV_ENABLED (Sdhci, i)) {

       continue;

     }