aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/qcom-msm8974.dtsi
blob: 753bdfddd46ea5d503c8409cc5c035b239efe47c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8974";
				qcom,smd-channels = "rpm_requests";

				pm8841-regulators {
					compatible = "qcom,rpm-pm8841-regulators";

					pm8841_s1: s1 {};
					pm8841_s2: s2 {};
					pm8841_s3: s3 {};
					pm8841_s4: s4 {};
					pm8841_s5: s5 {};
					pm8841_s6: s6 {};
					pm8841_s7: s7 {};
					pm8841_s8: s8 {};
				};

				pm8941-regulators {
					compatible = "qcom,rpm-pm8941-regulators";

					pm8941_s1: s1 {};
					pm8941_s2: s2 {};
					pm8941_s3: s3 {};
					pm8941_5v: s4 {};

					pm8941_l1: l1 {};
					pm8941_l2: l2 {};
					pm8941_l3: l3 {};
					pm8941_l4: l4 {};
					pm8941_l5: l5 {};
					pm8941_l6: l6 {};
					pm8941_l7: l7 {};
					pm8941_l8: l8 {};
					pm8941_l9: l9 {};
					pm8941_l10: l10 {};
					pm8941_l11: l11 {};
					pm8941_l12: l12 {};
					pm8941_l13: l13 {};
					pm8941_l14: l14 {};
					pm8941_l15: l15 {};
					pm8941_l16: l16 {};
					pm8941_l17: l17 {};
					pm8941_l18: l18 {};
					pm8941_l19: l19 {};
					pm8941_l20: l20 {};
					pm8941_l21: l21 {};
					pm8941_l22: l22 {};
					pm8941_l23: l23 {};
					pm8941_l24: l24 {};

					pm8941_lvs1: lvs1 {};
					pm8941_lvs2: lvs2 {};
					pm8941_lvs3: lvs3 {};

					pm8941_5vs1: 5vs1 {};
					pm8941_5vs2: 5vs2 {};
				};
			};
		};
	};
};