/* * Copyright © 2014 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #ifndef _INTEL_GUC_FWIF_H #define _INTEL_GUC_FWIF_H /* * This file is partially autogenerated, although currently with some manual * fixups afterwards. In future, it should be entirely autogenerated, in order * to ensure that the definitions herein remain in sync with those used by the * GuC's own firmware. * * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. */ #define GFXCORE_FAMILY_GEN8 11 #define GFXCORE_FAMILY_GEN9 12 #define GFXCORE_FAMILY_FORCE_ULONG 0x7fffffff #define GUC_CTX_PRIORITY_CRITICAL 0 #define GUC_CTX_PRIORITY_HIGH 1 #define GUC_CTX_PRIORITY_NORMAL 2 #define GUC_CTX_PRIORITY_LOW 3 #define GUC_MAX_GPU_CONTEXTS 1024 #define GUC_INVALID_CTX_ID (GUC_MAX_GPU_CONTEXTS + 1) /* Work queue item header definitions */ #define WQ_STATUS_ACTIVE 1 #define WQ_STATUS_SUSPENDED 2 #define WQ_STATUS_CMD_ERROR 3 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 #define WQ_TYPE_SHIFT 0 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) #define WQ_TARGET_SHIFT 10 #define WQ_LEN_SHIFT 16 #define WQ_NO_WCFLUSH_WAIT (1 << 27) #define WQ_PRESENT_WORKLOAD (1 << 28) #define WQ_WORKLOAD_SHIFT 29 #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) #define WQ_RING_TAIL_SHIFT 20 #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT) #define GUC_DOORBELL_ENABLED 1 #define GUC_DOORBELL_DISABLED 0 #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) #define GUC_CTX_DESC_ATTR_RESET (1 << 4) #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) #define GUC_CTX_DESC_ATTR_PCH (1 << 6) /* The guc control data is 10 DWORDs */ #define GUC_CTL_CTXINFO 0 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 #define GUC_CTL_BASE_ADDR_SHIFT 12 #define GUC_CTL_ARAT_HIGH 1 #define GUC_CTL_ARAT_LOW 2 #define GUC_CTL_DEVICE_INFO 3 #define GUC_CTL_GTTYPE_SHIFT 0 #define GUC_CTL_COREFAMILY_SHIFT 7 #define GUC_CTL_LOG_PARAMS 4 #define GUC_LOG_VALID (1 << 0) #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) #define GUC_LOG_CRASH_PAGES 1 #define GUC_LOG_CRASH_SHIFT 4 #define GUC_LOG_DPC_PAGES 3 #define GUC_LOG_DPC_SHIFT 6 #define GUC_LOG_ISR_PAGES 3 #define GUC_LOG_ISR_SHIFT 9 #define GUC_LOG_BUF_ADDR_SHIFT 12 #define GUC_CTL_PAGE_FAULT_CONTROL 5 #define GUC_CTL_WA 6 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) #define GUC_CTL_FEATURE 7 #define GUC_CTL_VCS2_ENABLED (1 << 0) #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) #define GUC_CTL_FEATURE2 (1 << 2) #define GUC_CTL_POWER_GATING (1 << 3) #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) #define GUC_CTL_PREEMPTION_LOG (1 << 5) #define GUC_CTL_ENABLE_SLPC (1 << 7) #define GUC_CTL_DEBUG 8 #define GUC_LOG_VERBOSITY_SHIFT 0 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) /* Verbosity range-check limits, without the shift */ #define GUC_LOG_VERBOSITY_MIN 0 #define GUC_LOG_VERBOSITY_MAX 3 #define GUC_CTL_MAX_DWORDS (GUC_CTL_DEBUG + 1) struct guc_doorbell_info { u32 db_status; u32 cookie; u32 reserved[14]; } __packed; union guc_doorbell_qw { struct { u32 db_status; u32 cookie; }; u64 value_qw; } __packed; #define GUC_MAX_DOORBELLS 256 #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) #define GUC_DB_SIZE (PAGE_SIZE) #define GUC_WQ_SIZE (PAGE_SIZE * 2) /* Work item for submitting workloads into work queue of GuC. */ struct guc_wq_item { u32 header; u32 context_desc; u32 ring_tail; u32 fence_id; } __packed; struct guc_process_desc { u32 context_id; u64 db_base_addr; u32 head; u32 tail; u32 error_offset; u64 wq_base_addr; u32 wq_size_bytes; u32 wq_status; u32 engine_presence; u32 priority; u32 reserved[30]; } __packed; /* engine id and context id is packed into guc_execlist_context.context_id*/ #define GUC_ELC_CTXID_OFFSET 0 #define GUC_ELC_ENGINE_OFFSET 29 /* The execlist context including software and HW information */ struct guc_execlist_context { u32 context_desc; u32 context_id; u32 ring_status; u32 ring_lcra; u32 ring_begin; u32 ring_end; u32 ring_next_free_location; u32 ring_current_tail_pointer_value; u8 engine_state_submit_value; u8 engine_state_wait_value; u16 pagefault_count; u16 engine_submit_queue_count; } __packed; /*Context descriptor for communicating between uKernel and Driver*/ struct guc_context_desc { u32 sched_common_area; u32 context_id; u32 pas_id; u8 engines_used; u64 db_trigger_cpu; u32 db_trigger_uk; u64 db_trigger_phy; u16 db_id; struct guc_execlist_context lrc[I915_NUM_RINGS]; u8 attribute; u32 priority; u32 wq_sampled_tail_offset; u32 wq_total_submit_enqueues; u32 process_desc; u32 wq_addr; u32 wq_size; u32 engine_presence; u32 reserved0[1]; u64 reserved1[1]; u64 desc_private; } __packed; /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ enum host2guc_action { HOST2GUC_ACTION_DEFAULT = 0x0, HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, HOST2GUC_ACTION_LIMIT }; /* * The GuC sends its response to a command by overwriting the * command in SS0. The response is distinguishable from a command * by the fact that all the MASK bits are set. The remaining bits * give more detail. */ #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) /* GUC will return status back to SOFT_SCRATCH_O_REG */ enum guc2host_status { GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) }; #endif