From c7c039fd31be82ecb8d48477955e76badd38141a Mon Sep 17 00:00:00 2001 From: Roy Spliet Date: Mon, 9 Jan 2012 15:23:07 +1000 Subject: drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet Signed-off-by: Martin Peres Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_pm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau/nouveau_pm.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c index 6e3851e1a1d7..8a742596d095 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/drivers/gpu/drm/nouveau/nouveau_pm.c @@ -808,6 +808,7 @@ nouveau_pm_init(struct drm_device *dev) ret = nouveau_pm_perflvl_get(dev, &pm->boot); if (ret == 0) { strncpy(pm->boot.name, "boot", 4); + pm->boot.timing = &pm->memtimings.boot; pm->cur = &pm->boot; nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info)); -- cgit v1.2.3