From e512448f6e98fb77f2be8ec7155f0ed941855796 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 23 Sep 2014 13:21:41 -0500 Subject: ARM: dts: qcom: Add SATA support on IPQ8064/AP148 Add SATA PHY and SATA AHCI controller nodes to device tree to enable generic ahci support on the IPQ8064/AP148 board. Signed-off-by: Kumar Gala --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 ++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 95e64955fb8e..55b2910efd87 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -81,5 +81,13 @@ }; }; }; + + sata-phy@1b400000 { + status = "ok"; + }; + + sata@29000000 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 244f857f0e6f..63b2146f563b 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -234,6 +234,39 @@ }; }; + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; + + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + + #phy-cells = <0>; + status = "disabled"; + }; + + sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <0 209 0x0>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; -- cgit v1.2.3