From 4ec07bba6945290c48dcc5b789cbd7adeabd7695 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 15:02:58 +0900 Subject: ARM: S3C2443: Use common clock gate code Add common clock gate code for each of the S3C2443 clock gate code. Whether to move this elsewhere will be decided later. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 48 ++++++++++++------------------------------- 1 file changed, 13 insertions(+), 35 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 3eb8b935d64c..5d061ea0c513 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -53,55 +53,33 @@ * set the correct muxing at initialisation */ -static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) +static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_HCLKCON); + u32 ctrlbit = clk->ctrlbit; + u32 con = __raw_readl(reg); if (enable) - clkcon |= clocks; + con |= ctrlbit; else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_HCLKCON); + con &= ~ctrlbit; + __raw_writel(con, reg); return 0; } -static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_PCLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_PCLKCON); + return s3c2443_gate(S3C2443_HCLKCON, clk, enable); +} - return 0; +static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +{ + return s3c2443_gate(S3C2443_PCLKCON, clk, enable); } static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) { - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2443_SCLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2443_SCLKCON); - - return 0; + return s3c2443_gate(S3C2443_SCLKCON, clk, enable); } static unsigned long s3c2443_roundrate_clksrc(struct clk *clk, -- cgit v1.2.3 From 9aa753c4422492547a190df8a3b6a56282669f9b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 09:19:59 +0200 Subject: ARM: S3C2443: Change to using plat-samsung clksrc-clk implementation The S3C2443 clock code could easily make use of the clksrc implementation in plat-samsung for many of the clocks. Make the clocks that easily move to clksrc-clk over, update any initialisation and remove the old register definitions from the header file (it is only being used once). Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/Kconfig | 1 + arch/arm/mach-s3c2443/clock.c | 513 +++++++++++------------------------------- 2 files changed, 127 insertions(+), 387 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index 4314c4424909..698140af247c 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2443 depends on ARCH_S3C2410 select S3C2443_DMA if S3C2410_DMA select CPU_LLSERIAL_S3C2440 + select SAMSUNG_CLKSRC help Support for the S3C2443 SoC from the S3C24XX line diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 5d061ea0c513..f89e71f50345 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s3c2443/clock.c * - * Copyright (c) 2007 Simtec Electronics + * Copyright (c) 2007,2010 Simtec Electronics * Ben Dooks * * S3C2443 Clock control support @@ -42,6 +42,7 @@ #include #include +#include #include /* We currently have to assume that the system is running @@ -82,45 +83,7 @@ static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) return s3c2443_gate(S3C2443_SCLKCON, clk, enable); } -static unsigned long s3c2443_roundrate_clksrc(struct clk *clk, - unsigned long rate, - unsigned int max) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations as they cancel out */ - - div = (rate / parent_rate); - - if (div < 1) - div = 1; - else if (div > max) - div = max; - - return parent_rate / div; -} - -static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk, - unsigned long rate) -{ - return s3c2443_roundrate_clksrc(clk, rate, 4); -} - -static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk, - unsigned long rate) -{ - return s3c2443_roundrate_clksrc(clk, rate, 16); -} - -static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk, - unsigned long rate) -{ - return s3c2443_roundrate_clksrc(clk, rate, 256); -} +/* s3c2443_roundate_clksrc is close enough to s3c_roundate_clksrc */ /* clock selections */ @@ -143,31 +106,23 @@ static struct clk clk_i2s_ext = { .id = -1, }; -static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); - - clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK; - - if (parent == &clk_xtal) - clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL; - else if (parent == &clk_ext) - clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK; - else if (parent != &clk_mpllref) - return -EINVAL; - - __raw_writel(clksrc, S3C2443_CLKSRC); - clk->parent = parent; - - return 0; -} +static struct clk *clk_epllref_sources[] = { + [0] = &clk_mpllref, + [1] = &clk_mpllref, + [2] = &clk_xtal, + [3] = &clk_ext, +}; -static struct clk clk_epllref = { - .name = "epllref", - .id = -1, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_epllref, +static struct clksrc_clk clk_epllref = { + .clk = { + .name = "epllref", + .id = -1, + }, + .sources = &(struct clksrc_sources) { + .sources = clk_epllref_sources, + .nr_sources = ARRAY_SIZE(clk_epllref_sources), }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, }; static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) @@ -273,7 +228,7 @@ static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent) if (parent == &clk_epll) clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL; - else if (parent == &clk_epllref) + else if (parent == &clk_epllref.clk) clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL; else return -EINVAL; @@ -298,87 +253,30 @@ static struct clk clk_esysclk = { * UART baud-rate clock sourced from esysclk via a divisor */ -static unsigned long s3c2443_getrate_uart(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_UARTDIV_MASK; - div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT; - - return parent_rate / (div + 1); -} - - -static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc16(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_uart = { - .name = "uartclk", - .id = -1, - .parent = &clk_esysclk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_uart, - .set_rate = s3c2443_setrate_uart, - .round_rate = s3c2443_roundrate_clksrc16, +static struct clksrc_clk clk_uart = { + .clk = { + .name = "uartclk", + .id = -1, + .parent = &clk_esysclk, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, }; + /* hsspi * * high-speed spi clock, sourced from esysclk */ -static unsigned long s3c2443_getrate_hsspi(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_HSSPIDIV_MASK; - div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT; - - return parent_rate / (div + 1); -} - - -static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc4(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_hsspi = { - .name = "hsspi", - .id = -1, - .parent = &clk_esysclk, - .ctrlbit = S3C2443_SCLKCON_HSSPICLK, - .enable = s3c2443_clkcon_enable_s, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_hsspi, - .set_rate = s3c2443_setrate_hsspi, - .round_rate = s3c2443_roundrate_clksrc4, +static struct clksrc_clk clk_hsspi = { + .clk = { + .name = "hsspi", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_HSSPICLK, + .enable = s3c2443_clkcon_enable_s, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, }; /* usbhost @@ -386,43 +284,15 @@ static struct clk clk_hsspi = { * usb host bus-clock, usually 48MHz to provide USB bus clock timing */ -static unsigned long s3c2443_getrate_usbhost(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK; - div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc4(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_usb_bus_host = { - .name = "usb-bus-host-parent", - .id = -1, - .parent = &clk_esysclk, - .ctrlbit = S3C2443_SCLKCON_USBHOST, - .enable = s3c2443_clkcon_enable_s, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_usbhost, - .set_rate = s3c2443_setrate_usbhost, - .round_rate = s3c2443_roundrate_clksrc4, +static struct clksrc_clk clk_usb_bus_host = { + .clk = { + .name = "usb-bus-host-parent", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_USBHOST, + .enable = s3c2443_clkcon_enable_s, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, }; /* clk_hsmcc_div @@ -432,41 +302,13 @@ static struct clk clk_usb_bus_host = { * be fed to the hsmmc block */ -static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_HSMMCDIV_MASK; - div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc4(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_hsmmc_div = { - .name = "hsmmc-div", - .id = -1, - .parent = &clk_esysclk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_hsmmc_div, - .set_rate = s3c2443_setrate_hsmmc_div, - .round_rate = s3c2443_roundrate_clksrc4, +static struct clksrc_clk clk_hsmmc_div = { + .clk = { + .name = "hsmmc-div", + .id = -1, + .parent = &clk_esysclk, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, }; static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) @@ -499,7 +341,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable) static struct clk clk_hsmmc = { .name = "hsmmc-if", .id = -1, - .parent = &clk_hsmmc_div, + .parent = &clk_hsmmc_div.clk, .enable = s3c2443_enable_hsmmc, .ops = &(struct clk_ops) { .set_parent = s3c2443_setparent_hsmmc, @@ -508,79 +350,46 @@ static struct clk clk_hsmmc = { /* i2s_eplldiv * - * this clock is the output from the i2s divisor of esysclk + * This clock is the output from the I2S divisor of ESYSCLK, and is seperate + * from the mux that comes after it (cannot merge into one single clock) */ -static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_I2SDIV_MASK; - div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc16(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_i2s_eplldiv = { - .name = "i2s-eplldiv", - .id = -1, - .parent = &clk_esysclk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_i2s_eplldiv, - .set_rate = s3c2443_setrate_i2s_eplldiv, - .round_rate = s3c2443_roundrate_clksrc16, +static struct clksrc_clk clk_i2s_eplldiv = { + .clk = { + .name = "i2s-eplldiv", + .id = -1, + .parent = &clk_esysclk, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, }; /* i2s-ref * * i2s bus reference clock, selectable from external, esysclk or epllref + * + * Note, this used to be two clocks, but was compressed into one. */ -static int s3c2443_setparent_i2s(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); - - clksrc &= ~S3C2443_CLKSRC_I2S_MASK; - - if (parent == &clk_epllref) - clksrc |= S3C2443_CLKSRC_I2S_EPLLREF; - else if (parent == &clk_i2s_ext) - clksrc |= S3C2443_CLKSRC_I2S_EXT; - else if (parent != &clk_i2s_eplldiv) - return -EINVAL; - - clk->parent = parent; - __raw_writel(clksrc, S3C2443_CLKSRC); +struct clk *clk_i2s_srclist[] = { + [0] = &clk_i2s_eplldiv.clk, + [1] = &clk_i2s_ext, + [2] = &clk_epllref.clk, + [3] = &clk_epllref.clk, +}; - return 0; -} +static struct clksrc_clk clk_i2s = { + .clk = { + .name = "i2s-if", + .id = -1, + .ctrlbit = S3C2443_SCLKCON_I2SCLK, + .enable = s3c2443_clkcon_enable_s, -static struct clk clk_i2s = { - .name = "i2s-if", - .id = -1, - .parent = &clk_i2s_eplldiv, - .ctrlbit = S3C2443_SCLKCON_I2SCLK, - .enable = s3c2443_clkcon_enable_s, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_i2s, }, + .sources = &(struct clksrc_sources) { + .sources = clk_i2s_srclist, + .nr_sources = ARRAY_SIZE(clk_i2s_srclist), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, }; /* cam-if @@ -588,43 +397,15 @@ static struct clk clk_i2s = { * camera interface bus-clock, divided down from esysclk */ -static unsigned long s3c2443_getrate_cam(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_CAMDIV_MASK; - div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc16(clk, rate); - rate = parent_rate / rate; - - clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK; - clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT; - - __raw_writel(clkdiv1, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_cam = { - .name = "camif-upll", /* same as 2440 name */ - .id = -1, - .parent = &clk_esysclk, - .ctrlbit = S3C2443_SCLKCON_CAMCLK, - .enable = s3c2443_clkcon_enable_s, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_cam, - .set_rate = s3c2443_setrate_cam, - .round_rate = s3c2443_roundrate_clksrc16, +static struct clksrc_clk clk_cam = { + .clk = { + .name = "camif-upll", /* same as 2440 name */ + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_CAMCLK, + .enable = s3c2443_clkcon_enable_s, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, }; /* display-if @@ -632,43 +413,15 @@ static struct clk clk_cam = { * display interface clock, divided from esysclk */ -static unsigned long s3c2443_getrate_display(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV1); - - div &= S3C2443_CLKDIV1_DISPDIV_MASK; - div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2443_setrate_display(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); - - rate = s3c2443_roundrate_clksrc256(clk, rate); - rate = parent_rate / rate; - - clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK; - clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2443_CLKDIV1); - return 0; -} - -static struct clk clk_display = { - .name = "display-if", - .id = -1, - .parent = &clk_esysclk, - .ctrlbit = S3C2443_SCLKCON_DISPCLK, - .enable = s3c2443_clkcon_enable_s, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_display, - .set_rate = s3c2443_setrate_display, - .round_rate = s3c2443_roundrate_clksrc256, +static struct clksrc_clk clk_display = { + .clk = { + .name = "display-if", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_DISPCLK, + .enable = s3c2443_clkcon_enable_s, }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, }; /* prediv @@ -865,7 +618,7 @@ static struct clk init_clocks[] = { }, { .name = "usb-bus-host", .id = -1, - .parent = &clk_usb_bus_host, + .parent = &clk_usb_bus_host.clk, }, { .name = "ac97", .id = -1, @@ -887,50 +640,27 @@ static int __init clk_init_set_parent(struct clk *clk, struct clk *parent) return clk_set_parent(clk, parent); } +static struct clksrc_clk __initdata *init_list[] = { + &clk_epllref, /* should be first */ + &clk_i2s_eplldiv, + &clk_i2s, + &clk_cam, + &clk_uart, + &clk_display, + &clk_hsmmc_div, + &clk_usb_bus_host, +}; + static void __init s3c2443_clk_initparents(void) { unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); struct clk *parent; - - switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) { - case S3C2443_CLKSRC_EPLLREF_EXTCLK: - parent = &clk_ext; - break; - - case S3C2443_CLKSRC_EPLLREF_XTAL: - default: - parent = &clk_xtal; - break; - - case S3C2443_CLKSRC_EPLLREF_MPLLREF: - case S3C2443_CLKSRC_EPLLREF_MPLLREF2: - parent = &clk_mpllref; - break; - } - - clk_init_set_parent(&clk_epllref, parent); - - switch (clksrc & S3C2443_CLKSRC_I2S_MASK) { - case S3C2443_CLKSRC_I2S_EXT: - parent = &clk_i2s_ext; - break; - - case S3C2443_CLKSRC_I2S_EPLLDIV: - default: - parent = &clk_i2s_eplldiv; - break; - - case S3C2443_CLKSRC_I2S_EPLLREF: - case S3C2443_CLKSRC_I2S_EPLLREF3: - parent = &clk_epllref; - } - - clk_init_set_parent(&clk_i2s, &clk_epllref); + int ptr; /* esysclk source */ parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ? - &clk_epll : &clk_epllref; + &clk_epll : &clk_epllref.clk; clk_init_set_parent(&clk_esysclk, parent); @@ -953,6 +683,9 @@ static void __init s3c2443_clk_initparents(void) parent = &clk_armdiv; clk_init_set_parent(&clk_arm, parent); + + for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++) + s3c_set_clksrc(init_list[ptr], false); } /* armdiv divisor table */ @@ -984,15 +717,9 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) /* clocks to add straight away */ -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_epll, +static struct clksrc_clk *clksrcs[] __initdata = { &clk_usb_bus_host, - &clk_usb_bus, - &clk_esysclk, &clk_epllref, - &clk_mpllref, - &clk_msysclk, &clk_uart, &clk_display, &clk_cam, @@ -1000,6 +727,15 @@ static struct clk *clks[] __initdata = { &clk_i2s, &clk_hsspi, &clk_hsmmc_div, +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_usb_bus, + &clk_esysclk, + &clk_mpllref, + &clk_msysclk, &clk_hsmmc, &clk_armdiv, &clk_arm, @@ -1064,15 +800,18 @@ void __init s3c2443_init_clocks(int xtal) } } + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_register_clksrc(clksrcs[ptr], 1); + clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - clk_epll.parent = &clk_epllref; - clk_usb_bus.parent = &clk_usb_bus_host; + clk_epll.parent = &clk_epllref.clk; + clk_usb_bus.parent = &clk_usb_bus_host.clk; /* ensure usb bus clock is within correct rate of 48MHz */ - if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) { + if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); - clk_set_rate(&clk_usb_bus_host, 48*1000*1000); + clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); } printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", -- cgit v1.2.3 From 4bed36b2c5b3248ae6f9aaf5194fbe85153e4026 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 10:25:49 +0200 Subject: ARM: S3C2443: Further clksrc-clk conversions Move more of the core clocks that where left over from the last commit as they are much more core to the system operation. This should allow for easier tracking of any problems. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 187 ++++++++++++++---------------------------- 1 file changed, 62 insertions(+), 125 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f89e71f50345..1307f69abf98 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s3c2443/clock.c * - * Copyright (c) 2007,2010 Simtec Electronics + * Copyright (c) 2007, 2010 Simtec Electronics * Ben Dooks * * S3C2443 Clock control support @@ -145,33 +145,24 @@ static struct clk clk_mdivclk = { }, }; -static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); - - clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL | - S3C2443_CLKSRC_EXTCLK_DIV); - - if (parent == &clk_mpll) - clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL; - else if (parent == &clk_mdivclk) - clksrc |= S3C2443_CLKSRC_EXTCLK_DIV; - else if (parent != &clk_mpllref) - return -EINVAL; - - __raw_writel(clksrc, S3C2443_CLKSRC); - clk->parent = parent; - - return 0; -} +static struct clk *clk_msysclk_sources[] = { + [0] = &clk_mpllref, + [1] = &clk_mpll, + [2] = &clk_mdivclk, + [3] = &clk_mpllref, +}; -static struct clk clk_msysclk = { - .name = "msysclk", - .parent = &clk_xtal, - .id = -1, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_msysclk, +static struct clksrc_clk clk_msysclk = { + .clk = { + .name = "msysclk", + .parent = &clk_xtal, + .id = -1, + }, + .sources = &(struct clksrc_sources) { + .sources = clk_msysclk_sources, + .nr_sources = ARRAY_SIZE(clk_msysclk_sources), }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, }; /* armdiv @@ -183,38 +174,29 @@ static struct clk clk_msysclk = { static struct clk clk_armdiv = { .name = "armdiv", .id = -1, - .parent = &clk_msysclk, + .parent = &clk_msysclk.clk, }; /* armclk * - * this is the clock fed into the ARM core itself, either from - * armdiv or from hclk. + * this is the clock fed into the ARM core itself, from armdiv or from hclk. */ -static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) -{ - unsigned long clkdiv0; - - clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - if (parent == &clk_armdiv) - clkdiv0 &= ~S3C2443_CLKDIV0_DVS; - else if (parent == &clk_h) - clkdiv0 |= S3C2443_CLKDIV0_DVS; - else - return -EINVAL; - - __raw_writel(clkdiv0, S3C2443_CLKDIV0); - return 0; -} +static struct clk *clk_arm_sources[] = { + [0] = &clk_armdiv, + [1] = &clk_h, +}; -static struct clk clk_arm = { - .name = "armclk", - .id = -1, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_armclk, +static struct clksrc_clk clk_arm = { + .clk = { + .name = "armclk", + .id = -1, }, + .sources = &(struct clksrc_sources) { + .sources = clk_arm_sources, + .nr_sources = ARRAY_SIZE(clk_arm_sources), + }, + .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, }; /* esysclk @@ -222,30 +204,22 @@ static struct clk clk_arm = { * this is sourced from either the EPLL or the EPLLref clock */ -static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); - - if (parent == &clk_epll) - clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL; - else if (parent == &clk_epllref.clk) - clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL; - else - return -EINVAL; - - __raw_writel(clksrc, S3C2443_CLKSRC); - clk->parent = parent; - - return 0; -} +static struct clk *clk_sysclk_sources[] = { + [0] = &clk_epllref.clk, + [1] = &clk_epll, +}; -static struct clk clk_esysclk = { - .name = "esysclk", - .parent = &clk_epll, - .id = -1, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_esysclk, +static struct clksrc_clk clk_esysclk = { + .clk = { + .name = "esysclk", + .parent = &clk_epll, + .id = -1, }, + .sources = &(struct clksrc_sources) { + .sources = clk_sysclk_sources, + .nr_sources = ARRAY_SIZE(clk_sysclk_sources), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, }; /* uartclk @@ -257,7 +231,7 @@ static struct clksrc_clk clk_uart = { .clk = { .name = "uartclk", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, }; @@ -272,7 +246,7 @@ static struct clksrc_clk clk_hsspi = { .clk = { .name = "hsspi", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_HSSPICLK, .enable = s3c2443_clkcon_enable_s, }, @@ -288,7 +262,7 @@ static struct clksrc_clk clk_usb_bus_host = { .clk = { .name = "usb-bus-host-parent", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_USBHOST, .enable = s3c2443_clkcon_enable_s, }, @@ -306,7 +280,7 @@ static struct clksrc_clk clk_hsmmc_div = { .clk = { .name = "hsmmc-div", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, }; @@ -358,7 +332,7 @@ static struct clksrc_clk clk_i2s_eplldiv = { .clk = { .name = "i2s-eplldiv", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, }; @@ -401,7 +375,7 @@ static struct clksrc_clk clk_cam = { .clk = { .name = "camif-upll", /* same as 2440 name */ .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_CAMCLK, .enable = s3c2443_clkcon_enable_s, }, @@ -417,7 +391,7 @@ static struct clksrc_clk clk_display = { .clk = { .name = "display-if", .id = -1, - .parent = &clk_esysclk, + .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_DISPCLK, .enable = s3c2443_clkcon_enable_s, }, @@ -443,7 +417,7 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk) static struct clk clk_prediv = { .name = "prediv", .id = -1, - .parent = &clk_msysclk, + .parent = &clk_msysclk.clk, .ops = &(struct clk_ops) { .get_rate = s3c2443_prediv_getrate, }, @@ -629,19 +603,11 @@ static struct clk init_clocks[] = { /* clocks to add where we need to check their parentage */ -/* s3c2443_clk_initparents - * - * Initialise the parents for the clocks that we get at start-time -*/ - -static int __init clk_init_set_parent(struct clk *clk, struct clk *parent) -{ - printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name); - return clk_set_parent(clk, parent); -} - static struct clksrc_clk __initdata *init_list[] = { &clk_epllref, /* should be first */ + &clk_esysclk, + &clk_msysclk, + &clk_arm, &clk_i2s_eplldiv, &clk_i2s, &clk_cam, @@ -653,39 +619,10 @@ static struct clksrc_clk __initdata *init_list[] = { static void __init s3c2443_clk_initparents(void) { - unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); - struct clk *parent; int ptr; - /* esysclk source */ - - parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ? - &clk_epll : &clk_epllref.clk; - - clk_init_set_parent(&clk_esysclk, parent); - - /* msysclk source */ - - if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) { - parent = &clk_mpll; - } else { - parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ? - &clk_mdivclk : &clk_mpllref; - } - - clk_init_set_parent(&clk_msysclk, parent); - - /* arm */ - - if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS) - parent = &clk_h; - else - parent = &clk_armdiv; - - clk_init_set_parent(&clk_arm, parent); - for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++) - s3c_set_clksrc(init_list[ptr], false); + s3c_set_clksrc(init_list[ptr], true); } /* armdiv divisor table */ @@ -720,6 +657,9 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) static struct clksrc_clk *clksrcs[] __initdata = { &clk_usb_bus_host, &clk_epllref, + &clk_esysclk, + &clk_msysclk, + &clk_arm, &clk_uart, &clk_display, &clk_cam, @@ -733,12 +673,9 @@ static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, &clk_usb_bus, - &clk_esysclk, &clk_mpllref, - &clk_msysclk, &clk_hsmmc, &clk_armdiv, - &clk_arm, &clk_prediv, }; @@ -758,7 +695,7 @@ void __init_or_cpufreq s3c2443_setup_clocks(void) clk_put(xtal_clk); pll = s3c2443_get_mpll(mpllcon, xtal); - clk_msysclk.rate = pll; + clk_msysclk.clk.rate = pll; fclk = pll / s3c2443_fclk_div(clkdiv0); hclk = s3c2443_prediv_getrate(&clk_prediv); -- cgit v1.2.3 From 2dd5f181420ae8ea1cb976b81ed87517f0d4fcd7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 10:46:52 +0200 Subject: ARM: S3C2443: Update notes on MPLLREF clock Add note on MPLLREF clock source and why it cannot be easily removed. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 1307f69abf98..3fa37aa62aab 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -83,10 +83,12 @@ static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) return s3c2443_gate(S3C2443_SCLKCON, clk, enable); } -/* s3c2443_roundate_clksrc is close enough to s3c_roundate_clksrc */ - /* clock selections */ +/* mpllref is a direct descendant of clk_xtal by default, but it is not + * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as + * such directly equating the two source clocks is impossible. + */ static struct clk clk_mpllref = { .name = "mpllref", .parent = &clk_xtal, -- cgit v1.2.3 From 71ed587d4a5d377ef5a6917043543ff949ff7dcf Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 10:49:15 +0200 Subject: ARM: S3C2443: Remove #if 0 for clk_mpll The clk_mpll has long been moved into common clock code, remove the code completely instead of the nasty #if 0 block. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 3fa37aa62aab..177719c7c267 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -95,14 +95,6 @@ static struct clk clk_mpllref = { .id = -1, }; -#if 0 -static struct clk clk_mpll = { - .name = "mpll", - .parent = &clk_mpllref, - .id = -1, -}; -#endif - static struct clk clk_i2s_ext = { .name = "i2s-ext", .id = -1, -- cgit v1.2.3 From 41f23a09f32124322dc41bea7f65baff6e9b0ac5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 30 Jan 2010 11:14:14 +0200 Subject: ARM: S3C2443: Add set_rate and round_rate calls for armdiv clock Add set_rate and round_rate calls to armdiv for future use with cpu frequency scaling. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2443/clock.c | 93 +++++++++++++++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-s3c2443') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 177719c7c267..62cd4eaee01b 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -165,10 +165,83 @@ static struct clksrc_clk clk_msysclk = { * divider values applied to it to then be fed into armclk. */ +/* armdiv divisor table */ + +static unsigned int armdiv[16] = { + [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, + [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, + [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, + [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, + [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, + [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, + [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, + [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, +}; + +static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) +{ + clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; + + return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; +} + +static unsigned long s3c2443_armclk_roundrate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + unsigned long calc; + unsigned best = 256; /* bigger than any value */ + unsigned div; + int ptr; + + for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) { + div = armdiv[ptr]; + calc = parent / div; + if (calc <= rate && div < best) + best = div; + } + + return parent / best; +} + +static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + unsigned long calc; + unsigned div; + unsigned best = 256; /* bigger than any value */ + int ptr; + int val = -1; + + for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) { + div = armdiv[ptr]; + calc = parent / div; + if (calc <= rate && div < best) { + best = div; + val = ptr; + } + } + + if (val >= 0) { + unsigned long clkcon0; + + clkcon0 = __raw_readl(S3C2443_CLKDIV0); + clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; + clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; + __raw_writel(clkcon0, S3C2443_CLKDIV0); + } + + return (val == -1) ? -EINVAL : 0; +} + static struct clk clk_armdiv = { .name = "armdiv", .id = -1, .parent = &clk_msysclk.clk, + .ops = &(struct clk_ops) { + .round_rate = s3c2443_armclk_roundrate, + .set_rate = s3c2443_armclk_setrate, + }, }; /* armclk @@ -619,26 +692,6 @@ static void __init s3c2443_clk_initparents(void) s3c_set_clksrc(init_list[ptr], true); } -/* armdiv divisor table */ - -static unsigned int armdiv[16] = { - [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, - [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, - [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, - [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, - [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, - [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, - [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, - [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, -}; - -static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) -{ - clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; - - return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; -} - static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) { clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; -- cgit v1.2.3