From 3fa2252b7a78a8057017471a28f47b306e95ee26 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 15 Jan 2014 10:47:22 -0800 Subject: clk: Add set_rate_and_parent() op Some of Qualcomm's clocks can change their parent and rate at the same time with a single register write. Add support for this hardware to the common clock framework by adding a new set_rate_and_parent() op. When the clock framework determines that both the parent and the rate are going to change during clk_set_rate() it will call the .set_rate_and_parent() op if available and fall back to calling .set_parent() followed by .set_rate() otherwise. Reviewed-by: James Hogan Signed-off-by: Stephen Boyd Signed-off-by: Mike Turquette --- Documentation/clk.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/clk.txt') diff --git a/Documentation/clk.txt b/Documentation/clk.txt index eb20198783cd..699ef2a323b1 100644 --- a/Documentation/clk.txt +++ b/Documentation/clk.txt @@ -77,6 +77,9 @@ the operations defined in clk.h: int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long); + int (*set_rate_and_parent)(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); void (*init)(struct clk_hw *hw); -- cgit v1.2.3