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Wishbone is an open hardware SoC bus commonly used in FPGA
designs. Bus access can be serialized using the Etherbone
protocol <http://www.ohwr.org/projects/etherbone-core>.
This driver is intended to be used with devices which attach
their internal Wishbone bus to a USB serial interface using
the Etherbone protocol. A userspace library is required to
speak the protocol made available by this driver as ttyUSBx.
Signed-off-by: Wesley W. Terpstra <w.terpstra@gsi.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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