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2013-04-12ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller ↵Philipp Zabel
(SRC) The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12dt: describe base reset signal bindingStephen Warren
This binding is intended to represent the hardware reset signals present internally in most IC (SoC, FPGA, ...) designs. It consists of a binding for a reset controller device (provider), and a pair of properties, "resets" and "reset-names", to link a device node (consumer) to its reset controller via phandle, similarly to the clock and interrupt bindings. The reset controller has all information necessary to reset the consumer device. That could be provided via device tree, or it could be implemented in hardware. The aim is to enable device drivers to request a framework API to issue a reset simply by providing their struct device pointer as the most common case. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Acked-by: Rob Herring <rob.herring@calxeda.com>