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2014-05-21word-at-a-time: simplify big-endian zero_bytemask macrov3.10/topic/arm64-beH. Peter Anvin
This is simpler and cleaner. Depending on architecture, a smart compiler may or may not generate the same code. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 789ce9dca8007ab5d7c72b9a174a29243817ac32) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21word-at-a-time: avoid undefined behaviour in zero_bytemask macroWill Deacon
The asm-generic, big-endian version of zero_bytemask creates a mask of bytes preceding the first zero-byte by left shifting ~0ul based on the position of the first zero byte. Unfortunately, if the first (top) byte is zero, the output of prep_zero_mask has only the top bit set, resulting in undefined C behaviour as we shift left by an amount equal to the width of the type. As it happens, GCC doesn't manage to spot this through the call to fls(), but the issue remains if architectures choose to implement their shift instructions differently. An example would be arch/arm/ (AArch32), where LSL Rd, Rn, #32 results in Rd == 0x0, whilst on arch/arm64 (AArch64) LSL Xd, Xn, #64 results in Xd == Xn. Rather than check explicitly for the problematic shift, this patch adds an extra shift by 1, replacing fls with __fls. Since zero_bytemask is never called with a zero argument (has_zero() is used to check the data first), we don't need to worry about calling __fls(0), which is undefined. Cc: <stable@vger.kernel.org> Cc: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit ec6931b281797b69e6cf109f9cc94d5a2bf994e0) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21word-at-a-time: provide generic big-endian zero_bytemask implementationWill Deacon
Whilst architectures may be able to do better than this (which they can, by simply defining their own macro), this is a generic stab at a zero_bytemask implementation for the asm-generic, big-endian word-at-a-time implementation. On arm64, a clz instruction is used to implement the fls efficiently. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 11ec50caedb56e3a87715edeff6a1852e6ae5416) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-03-14Merge branches 'v3.10/topic/be' and 'v3.10/topic/arm64-be' of ↵Mark Brown
git://git.linaro.org/kernel/linux-linaro-stable into lsk-v3.10-arm64-be
2014-03-14Merge branch 'linux-linaro-lsk-v3.10/be/32/core-20140413' of ↵v3.10/topic/old-arm64-bev3.10/topic/beMark Brown
git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be into lsk-v3.10-be
2014-03-13arm64: ptrace: fix compat registes get/set to be endian cleanMatthew Leach
On a BE system the wrong half of the X registers is retrieved/written when attempting to get/set the value of aarch32 registers through ptrace. Ensure that types are the correct width so that the relevant casting occurs. Signed-off-by: Matthew Leach <matthew.leach@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 6a2e5e521c333a0b56cb60dc5587e3f90859c5e7) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: module: ensure instruction is little-endian before manipulationWill Deacon
Relocations that require an instruction immediate to be re-encoded must ensure that the instruction pattern is represented in a little-endian format for the manipulation code to work correctly. This patch converts the loaded instruction into native-endianess prior to encoding and then converts back to little-endian byteorder before updating memory. Signed-off-by: Will Deacon <will.deacon@arm.com> Tested-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 122e2fa0d310d262cb85cf0b003032e5d2bc2ae7) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: kconfig: allow CPU_BIG_ENDIAN to be selectedWill Deacon
This patch wires up CONFIG_CPU_BIG_ENDIAN for the AArch64 kernel configuration. Selecting this option builds a big-endian kernel which can boot into a big-endian userspace. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a872013d6d03ab63736a01dcd9747580be3a6b70) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: big-endian: write CPU holding pen address as LEMatthew Leach
Currently when CPUs are brought online via a spin-table, the address they should jump to is written to the cpu-release-addr in the kernel's native endianness. As the kernel may switch endianness, secondaries might read the value byte-reversed from what was intended, and they would jump to the wrong address. As the only current arm64 spin-table implementations are little-endian, stricten up the arm64 spin-table definition such that the value written to cpu-release-addr is _always_ little-endian regardless of the endianness of any CPU. If a spinning CPU is operating big-endian, it must byte-reverse the value before jumping to handle this. Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 710be9ac4ea0d2e02a2c4aa625795e65bf3db5b1) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: big-endian: set correct endianess on kernel entryMatthew Leach
The endianness of memory accesses at EL2 and EL1 are configured by SCTLR_EL2.EE and SCTLR_EL1.EE respectively. When the kernel is booted, the state of SCTLR_EL{2,1}.EE is unknown, and thus the kernel must ensure that they are set before performing any memory accesses. This patch ensures that SCTLR_EL{2,1} are configured appropriately at boot for kernels of either endianness. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> [catalin.marinas@arm.com: fix SCTLR_EL1.E0E bit setting in head.S] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9cf71728931a4073b9e3a4bcbf9dada86bc98370) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: head: create a new function for setting the boot_cpu_mode flagMatthew Leach
Currently, the code for setting the __cpu_boot_mode flag is munged in with el2_setup. This makes things difficult on a BE bringup as a memory access has to have occurred before el2_setup which is the place that we'd like to set the endianess on the current EL. Create a new function for setting __cpu_boot_mode and have el2_setup return the mode the CPU. Also define a new constant in virt.h, BOOT_CPU_MODE_EL1, for readability. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 828e9834e9a5b7e61046aa3c5f603a4fecba2fb4) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: asm: add CPU_LE & CPU_BE assembler helpersMatthew Leach
Add CPU_LE and CPU_BE to select assembler code in little and big endian configurations respectively. Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit e68bedaa03c950ae8045e7899e7a6b2a97d1bf41) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: big-endian: don't treat code as data when copying sigret codeMatthew Leach
Currently the sigreturn compat code is copied to an offset in the vectors table. When using a BE kernel this data will be stored in the wrong endianess so when returning from a signal on a 32-bit BE system, arbitrary code will be executed. Instead of declaring the code inside a struct and copying that, use the assembler's .byte directives to store the code in the correct endianess regardless of platform endianess. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a1d5ebaf8ccdd100f45042ce32c591867de04ac3) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: compat: correct register concatenation for syscall wrappersMatthew Leach
The arm64 port contains wrappers for arm32 syscalls that pass 64-bit values. These wrappers concatenate the two registers to hold a 64-bit value in a single X register. On BE, however, the lower and higher words are swapped. Create a new assembler macro, regs_to_64, that when on BE systems swaps the registers in the orr instruction. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 55b89540b0d8d031f90e3d711ec0df3f797ecc61) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: compat: add support for big-endian (BE8) AArch32 binariesWill Deacon
This patch adds support for BE8 AArch32 tasks to the compat layer. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a795a38eb91cf72c4a05e72a9c84e317ee179a48) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm64/include/asm/elf.h
2014-03-13arm64: setup: report ELF_PLATFORM as the machine for utsnameWill Deacon
uname -m reports the machine field from the current utsname, which should reflect the endianness of the system. This patch reports ELF_PLATFORM for the field, so that everything appears consistent from userspace. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 94ed1f2cb5d46533f10262b1b760db7dbec9cf10) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: ELF: add support for big-endian executablesWill Deacon
This patch adds support for the aarch64_be ELF format to the AArch64 ELF loader. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 5436b5c8305b4ed37c5d11f96c1aaccca63c9ab2) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: big-endian: fix byteorder includeWill Deacon
For big-endian processors, we must include linux/byteorder/big_endian.h to get the relevant definitions for swabbing between CPU order and a defined endianness. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit c194520ada7c8f2eddec5ebf24982483b49736a0) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: big-endian: add big-endian support to top-level arch MakefileWill Deacon
This patch adds big-endian support to the AArch64 top-level Makefile. This currently just passes the relevant flags to the toolchain and is predicated on a Kconfig option that will be introduced later on. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a0974e6e217aead196033d72f898e2acb575304d) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13net: smc91x: dont't use SMC_outw for fixing up halfword-aligned dataWill Deacon
SMC_outw invokes an endian-aware I/O accessor, which may change the data endianness before writing to the device. This is not suitable for data transfers where the memory buffer is simply a string of bytes that does not require any byte-swapping. This patches fixes the smc91x SMC_PUSH_DATA macro so that it uses the string I/O accessor for outputting the leading or trailing halfwords on halfword-aligned buffers. Cc: <netdev@vger.kernel.org> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: David S. Miller <davem@davemloft.net> Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit e9e4ea74f06635f2ffc1dffe5ef40c854faa0a90) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13arm64: use correct register width when retrieving ASIDMatthew Leach
The ASID is represented as an unsigned int in mm_context_t and we currently use the mmid assembler macro to access this element of the struct. This should be accessed with a register of 32-bit width. If the incorrect register width is used the ASID will be returned in bits[32:63] of the register when running under big-endian. Fix a use of the mmid macro in tlb.S to use a 32-bit access. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit fc18047c732f6becba92618a397555927687efd3) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: cci driver need big endian fixes in asm codeVictor Kamensky
cci_enable_port_for_self written in asm and it works with h/w registers that are in little endian format. When run in big endian mode it needs byteswaped constants before/after it writes/reads to/from such registers Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit fdb07aee0b2b9d7d1893c97f5ce79ec355caaf1f) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: tlb: ASID macro should give 32bit result for BE correct operationVictor Kamensky
In order for ASID macro to be used as expression passed to inline asm as 'r' operand it needs to give 32 bit unsigned result, not unsigned 64bit expression. Otherwise when 64bit ASID is passed to inline assembler statement as 'r' operand (32bit) compiler behavior is not well specified. For example when __flush_tlb_mm function compiled in big endian case, and ASID is passed to tlb_op macro directly, 0 will be passed as 'mcr 15, 0, r4, cr8, cr3, {2}' argument in r4, unless ASID macro changed to produce 32 bit result. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit a1af3474487cc3b8731b990dceac6b6aad7f3ed8) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: mcpm: fix big endian issue in mcpm startup codeVictor Kamensky
In big endian mode mcpm_entry_point is first function that called on secondaries CPU. First it should switch CPU into big endian code. [ben.dooks@codethink.co.uk: merge fix patch from Victor into this] Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 519ceb9fd10cd7e836d0aa97b2068cc9e97f463b) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: signal: sigreturn_codes should be endian neutral to work in BE8Victor Kamensky
In case of BE8 kernel data is in BE order whereas code stays in LE order. Move sigreturn_codes to separate .S file and use proper assembler mnemonics for these code snippets. In this case compiler will take care of proper instructions byteswaps for BE8 case. Change assumes that sufficiently Thumb-capable tools are used to build kernel. Problem was discovered during ltp testing of BE system: all rt_sig* tests failed. Tested against the same tests in both BE and LE modes. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 574e2b5111e13827da501771b27d92e6e3f2e3d7) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm/kernel/Makefile
2014-03-13ARM: atomic64: fix endian-ness in atomic.hVictor Kamensky
Fix inline asm for atomic64_xxx functions in arm atomic.h. Instead of %H operand specifiers code should use %Q for least significant part of the value, and %R for the most significant part of the value. %H always returns the higher of the two register numbers, and therefore it is not endian neutral. %H should be used with ldrexd and strexd instructions. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 2245f92498b216b50e744423bde17626287409d8) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: kdgb: use <asm/opcodes.h> for data to be assembled as intructionBen Dooks
The arch_kgdb_breakpoint() function uses an inline assembly directive to assemble a specific instruction using .word. This means the linker will not treat is as an instruction, and therefore incorrectly swap the endian-ness if running BE8. As noted, this code means that kgdb is really only usable on arm32 kernels, and should be made dependant on not being a thumb2 kernel until fixed. However this is not something to be added to this patch. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> (cherry picked from commit 5a8b93fc9457be90adfa10d3df6497393c5e2dc2) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: Correct BUG() assembly to ensure it is endian-agnosticBen Dooks
Currently BUG() uses .word or .hword to create the necessary illegal instructions. However if we are building BE8 then these get swapped by the linker into different illegal instructions in the text. This means that the BUG() macro does not get trapped properly. Change to using <asm/opcodes.h> to provide the necessary ARM instruction building as we cannot rely on gcc/gas having the `.inst` instructions which where added to try and resolve this issue (reported by Dave Martin <Dave.Martin@arm.com>). Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> (cherry picked from commit 63328070eff2f4fd730c86966a0dbc976147c39f) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: net: fix arm instruction endian-ness in bpf_jit_32.cBen Dooks
Use <asm/opcodes.h> to correctly transform instruction byte ordering into in-memory ordering. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> (cherry picked from commit 3460743e025addc1ecbd496db2231181a2431774) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: hardware: fix endian-ness in <hardware/coresight.h>Ben Dooks
The <hardware/coresight.h> needs to take into account the endian-ness of the processor when reading and writing data, so change to using the readl/writel relaxed variants from the raw ones. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit bfdef3b32d2f36bf137c039de9a545cdfcfbafe2) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: set --be8 when linking modulesBen Dooks
To avoid having to make every text section swap the instruction order of all instructions, make sure modules are built also built with --be8 (as is the current kernel final link). If we do not do this, we would end up having to swap all instructions when loading a module, instead of just the instructions that we are applying ELF relocations to. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> (cherry picked from commit 0ab89d0bf8054c3146ec06df357946bb87f36729) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: module: correctly relocate instructions in BE8Ben Dooks
When in BE8 mode, our instructions are not in the same ordering as the data, so use <asm/opcodes.h> to take this into account. Note, also requires modules to be built --be8 Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> (cherry picked from commit f592d323bc2353db871d1e840f05b27e0730fb10) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: traps: use <asm/opcodes.h> to get correct instruction orderBen Dooks
The trap handler needs to take into account the endian configuration of the system when loading instructions. Use <asm/opcodes.h> to provide the necessary conversion functions. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (cherry picked from commit a79a0cb1d35ec422dcf493cef1bebf9fdfcfdb9a) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: alignment: correctly decode instructions in BE8 mode.Ben Dooks
If we are in BE8 mode, we must deal with the instruction stream being in LE order when data is being loaded in BE order. Ensure the data is swapped before processing to avoid thre following: Change to using <asm/opcodes.h> to provide the necessary conversion functions to change the byte ordering. This stops the following warning messages from the kernel on a fault: Unhandled fault: alignment exception (0x001) at 0xbfa09567 Alignment trap: not handling instruction 030091e8 at [<80333e8c>] Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (cherry picked from commit 8592edf0dec8159fde379eb7e056eaddbbd697f2) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: vexpress: add big endian supportBen Dooks
Add support for the versatile express systems to boot big-endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 98dec91fa36a4a74f7c44dd2dfb000203656f4f4) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: mvebu: support running big-endianBen Dooks
Add indication we can run these cores in BE mode, and ensure that the secondary CPU is set to big-endian mode in the initialisation code as the initial code runs little-endian. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> (cherry picked from commit bca028e7c2537fea9f401c20dd7b2103358b5efe) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm/mach-mvebu/headsmp.S
2014-03-13ARM: highbank: enable big-endianBen Dooks
Apart from a xgmac driver issue, the highbank seems to work correctly in big-endian mode. Allow the selection of big-endian in the system. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Rob Herring <rob.herring@calxeda.com> (cherry picked from commit 50eec2fce45ed48575f1c0582b748e409da08511) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: smp_scu: data endian fixesBen Dooks
The smp_scu driver needs to use the relaxed readl/write accessors to avoid any issues with the endian mode the processor core is in. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 099a4809133dc6548d37cc143ab0cb9c2eba97bb) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: twd: data endian fixBen Dooks
Ensure the twd driver uses the correct calls to access the hardware to ensure that we do not end up with data in the wrong endian format. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 2e874ea342146130206f8b39f2103f33690a7547) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm/kernel/smp_twd.c
2014-03-13ARM: pl01x debug code endian fixBen Dooks
The PL01X debug code needs to take into account which endian mode the processor is running in. If it is big-endian, ensure the data is swapped appropriately. Note, we could do this slightly more efficiently if we have an macro to do the necessary swap for the bits used by test. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 76e3faf156fa95b6465e747d702b94faf67117fc) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm/include/debug/pl01x.S
2014-03-13ARM: set BE8 if LE in head codeBen Dooks
If we are booting in LE and compiled for BE8, then add code to set the state to bE8. Since the instruction stream is always LE, we do not need to do anything special to the instruction. Also ensure that the secondary processors are started in the same mode. Note, we do add about 20 bytes to the kernel image, but it seems easier to do this than adding another configuration to change. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (cherry picked from commit 97bcb0fea590d3d704f985bec08f342d28992634) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Conflicts: arch/arm/kernel/sleep.S
2014-03-13ARM: fixup_pv_table bug when CPU_ENDIAN_BE8Ben Dooks
The fixup_pv_table assumes that the instructions are in the same endian configuration as the data, but when the CPU is running in BE8 the instructions stay in little-endian format. Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the alterations to the instructions taking in to account the LDR/STR will be swapping the data endian-ness. Since the code is only modifying a byte, we avoid dual-swapping the data, and just change the bits we clear and ORR in (in the case where the code is not thumb2). For thumb2, we add the necessary rev16 instructions to ensure that the instructions are processed in the correct format, as it was easier than re-writing the code to contain a mask and shift. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (cherry picked from commit 2f9bf9beddb1649485b47302a5aba9761cbc9084) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: asm: Add ARM_BE8() assembly helperBen Dooks
Add ARM_BE8() helper to wrap any code conditional on being compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert existing places where this is to use it. Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit 457c2403c513c74f60d5757fd11ae927e5554a38) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-13ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIANBen Dooks
The Kconfig for arch/arm/mach-ixp4xx has a local definition of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere. This means that if IXP4xx is selected and this symbol is selected eleswhere then an warning is produced. Clean the following error up by making the symbol be selected by the main ARCH_IXP4XX definition and have a common definition in arch/arm/mm/Kconfig warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX) warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX) Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> (cherry picked from commit d10d2d485497cdc62a7660cd981f8f1ae0dffe7d) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
2014-03-09Merge tag 'v3.10.33' into linux-linaro-lskMark Brown
This is the 3.10.33 stable release
2014-03-06Linux 3.10.33v3.10.33Greg Kroah-Hartman
2014-03-06ioat: fix tasklet tear downDan Williams
commit da87ca4d4ca101f177fffd84f1f0a5e4c0343557 upstream. Since commit 77873803363c "net_dma: mark broken" we no longer pin dma engines active for the network-receive-offload use case. As a result the ->free_chan_resources() that occurs after the driver self test no longer has a NET_DMA induced ->alloc_chan_resources() to back it up. A late firing irq can lead to ksoftirqd spinning indefinitely due to the tasklet_disable() performed by ->free_chan_resources(). Only ->alloc_chan_resources() can clear this condition in affected kernels. This problem has been present since commit 3e037454bcfa "I/OAT: Add support for MSI and MSI-X" in 2.6.24, but is now exposed. Given the NET_DMA use case is deprecated we can revisit moving the driver to use threaded irqs. For now, just tear down the irq and tasklet properly by: 1/ Disable the irq from triggering the tasklet 2/ Disable the irq from re-arming 3/ Flush inflight interrupts 4/ Flush the timer 5/ Flush inflight tasklets References: https://lkml.org/lkml/2014/1/27/282 https://lkml.org/lkml/2014/2/19/672 Cc: Ingo Molnar <mingo@elte.hu> Cc: Steven Rostedt <rostedt@goodmis.org> Reported-by: Mike Galbraith <bitbucket@online.de> Reported-by: Stanislav Fomichev <stfomichev@yandex-team.ru> Tested-by: Mike Galbraith <bitbucket@online.de> Tested-by: Stanislav Fomichev <stfomichev@yandex-team.ru> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-03-06drm/radeon: disable pll sharing for DP on DCE4.1Alex Deucher
commit 9ef4e1d000a5b335fcebfcf8aef3405e59574c89 upstream. Causes display problems. We had already disabled sharing for non-DP displays. Based on a patch from: Niels Ole Salscheider <niels_ole@salscheider-online.de> bug: https://bugzilla.kernel.org/show_bug.cgi?id=58121 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-03-06drm/radeon: fix missing bo reservationChristian König
commit 5e386b574cf7e1593e1296e5b0feea4108ed6ad8 upstream. Otherwise we might get a crash here. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-03-06drm/radeon: print the supported atpx function maskAlex Deucher
commit 9f050c7f9738ffa746c63415136645ad231b1348 upstream. Print the supported functions mask in addition to the version. This is useful in debugging PX problems since we can see what functions are available. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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