1 files changed, 77 insertions, 139 deletions

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
index 8cc87103a369..eafa87886643 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
@@ -31,74 +31,51 @@
 #include <nvif/class.h>
 #include <nvif/unpack.h>
 
-int
-nv04_fifo_context_attach(struct nvkm_object *parent,
-			 struct nvkm_object *object)
-{
-	nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid;
-	return 0;
-}
-
 void
-nv04_fifo_object_detach(struct nvkm_object *parent, int cookie)
+nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)
 {
-	struct nv04_fifo *fifo = (void *)parent->engine;
-	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
-	mutex_lock(&nv_subdev(fifo)->mutex);
+	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
+	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
 	nvkm_ramht_remove(imem->ramht, cookie);
-	mutex_unlock(&nv_subdev(fifo)->mutex);
 }
 
-int
-nv04_fifo_object_attach(struct nvkm_object *parent,
-			struct nvkm_object *object, u32 handle)
+static int
+nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
+			  struct nvkm_object *object)
 {
-	struct nv04_fifo *fifo = (void *)parent->engine;
-	struct nv04_fifo_chan *chan = (void *)parent;
-	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
-	u32 context, chid = chan->base.chid;
-	int ret;
-
-	if (nv_iclass(object, NV_GPUOBJ_CLASS))
-		context = nv_gpuobj(object)->addr >> 4;
-	else
-		context = 0x00000004; /* just non-zero */
-
-	if (object->engine) {
-		switch (nv_engidx(object->engine)) {
-		case NVDEV_ENGINE_DMAOBJ:
-		case NVDEV_ENGINE_SW:
-			context |= 0x00000000;
-			break;
-		case NVDEV_ENGINE_GR:
-			context |= 0x00010000;
-			break;
-		case NVDEV_ENGINE_MPEG:
-			context |= 0x00020000;
-			break;
-		default:
-			return -EINVAL;
-		}
+	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
+	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
+	u32 context = 0x80000000 | chan->base.chid << 24;
+	u32 handle  = object->handle;
+	int hash;
+
+	switch (object->engine->subdev.index) {
+	case NVDEV_ENGINE_DMAOBJ:
+	case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
+	case NVDEV_ENGINE_GR    : context |= 0x00010000; break;
+	case NVDEV_ENGINE_MPEG  : context |= 0x00020000; break;
+	default:
+		WARN_ON(1);
+		return -EINVAL;
 	}
 
-	context |= 0x80000000; /* valid */
-	context |= chid << 24;
-
-	mutex_lock(&nv_subdev(fifo)->mutex);
-	ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context);
-	mutex_unlock(&nv_subdev(fifo)->mutex);
-	return ret;
+	mutex_lock(&chan->fifo->base.engine.subdev.mutex);
+	hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,
+				 handle, context);
+	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
+	return hash;
 }
 
-int
-nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend)
+void
+nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
 {
-	struct nv04_fifo *fifo = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
+	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
+	struct nv04_fifo *fifo = chan->fifo;
 	struct nvkm_device *device = fifo->base.engine.subdev.device;
 	struct nvkm_memory *fctx = device->imem->ramfc;
 	struct ramfc_desc *c;
 	unsigned long flags;
+	u32 mask = fifo->base.nr - 1;
 	u32 data = chan->ramfc;
 	u32 chid;
 
@@ -107,7 +84,7 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
 
 	/* if this channel is active, replace it with a null context */
-	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max;
+	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask;
 	if (chid == chan->base.chid) {
 		nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
@@ -129,7 +106,7 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 
 		nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);
 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);
-		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
+		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask);
 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
 		nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
 	}
@@ -138,35 +115,26 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend)
 	nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
 	spin_unlock_irqrestore(&fifo->base.lock, flags);
-
-	return nvkm_fifo_channel_fini(&chan->base, suspend);
 }
 
-int
-nv04_fifo_chan_init(struct nvkm_object *object)
+void
+nv04_fifo_dma_init(struct nvkm_fifo_chan *base)
 {
-	struct nv04_fifo *fifo = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
+	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
+	struct nv04_fifo *fifo = chan->fifo;
 	struct nvkm_device *device = fifo->base.engine.subdev.device;
 	u32 mask = 1 << chan->base.chid;
 	unsigned long flags;
-	int ret;
-
-	ret = nvkm_fifo_channel_init(&chan->base);
-	if (ret)
-		return ret;
-
 	spin_lock_irqsave(&fifo->base.lock, flags);
 	nvkm_mask(device, NV04_PFIFO_MODE, mask, mask);
 	spin_unlock_irqrestore(&fifo->base.lock, flags);
-	return 0;
 }
 
-void
-nv04_fifo_chan_dtor(struct nvkm_object *object)
+void *
+nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
 {
-	struct nv04_fifo *fifo = (void *)object->engine;
-	struct nv04_fifo_chan *chan = (void *)object;
+	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
+	struct nv04_fifo *fifo = chan->fifo;
 	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
 	struct ramfc_desc *c = fifo->ramfc_desc;
 
@@ -175,22 +143,30 @@ nv04_fifo_chan_dtor(struct nvkm_object *object)
 		nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);
 	} while ((++c)->bits);
 	nvkm_done(imem->ramfc);
-
-	nvkm_fifo_channel_destroy(&chan->base);
+	return chan;
 }
 
+const struct nvkm_fifo_chan_func
+nv04_fifo_dma_func = {
+	.dtor = nv04_fifo_dma_dtor,
+	.init = nv04_fifo_dma_init,
+	.fini = nv04_fifo_dma_fini,
+	.object_ctor = nv04_fifo_dma_object_ctor,
+	.object_dtor = nv04_fifo_dma_object_dtor,
+};
+
 static int
-nv04_fifo_chan_ctor(struct nvkm_object *parent,
-		    struct nvkm_object *engine,
-		    struct nvkm_oclass *oclass, void *data, u32 size,
-		    struct nvkm_object **pobject)
+nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
+		  void *data, u32 size, struct nvkm_object **pobject)
 {
+	struct nvkm_object *parent = oclass->parent;
 	union {
 		struct nv03_channel_dma_v0 v0;
 	} *args = data;
-	struct nv04_fifo *fifo = (void *)engine;
-	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
-	struct nv04_fifo_chan *chan;
+	struct nv04_fifo *fifo = nv04_fifo(base);
+	struct nv04_fifo_chan *chan = NULL;
+	struct nvkm_device *device = fifo->base.engine.subdev.device;
+	struct nvkm_instmem *imem = device->imem;
 	int ret;
 
 	nvif_ioctl(parent, "create channel dma size %d\n", size);
@@ -198,29 +174,32 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent,
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 				   "offset %08x\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
+		if (!args->v0.pushbuf)
+			return -EINVAL;
 	} else
 		return ret;
 
-	ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
-				       0x10000, args->v0.pushbuf,
-				       (1ULL << NVDEV_ENGINE_DMAOBJ) |
-				       (1ULL << NVDEV_ENGINE_SW) |
-				       (1ULL << NVDEV_ENGINE_GR), &chan);
-	*pobject = nv_object(chan);
+	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
+		return -ENOMEM;
+	*pobject = &chan->base.object;
+
+	ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
+				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
+				  (1ULL << NVDEV_ENGINE_DMAOBJ) |
+				  (1ULL << NVDEV_ENGINE_GR) |
+				  (1ULL << NVDEV_ENGINE_SW),
+				  0, 0x800000, 0x10000, oclass, &chan->base);
+	chan->fifo = fifo;
 	if (ret)
 		return ret;
 
 	args->v0.chid = chan->base.chid;
-
-	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
-	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
-	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
 	chan->ramfc = chan->base.chid * 32;
 
 	nvkm_kmap(imem->ramfc);
 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
-	nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4);
+	nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);
 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x10,
 			       NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 			       NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
@@ -232,51 +211,10 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent,
 	return 0;
 }
 
-static struct nvkm_ofuncs
-nv04_fifo_ofuncs = {
-	.ctor = nv04_fifo_chan_ctor,
-	.dtor = nv04_fifo_chan_dtor,
-	.init = nv04_fifo_chan_init,
-	.fini = nv04_fifo_chan_fini,
-	.map  = _nvkm_fifo_channel_map,
-	.rd32 = _nvkm_fifo_channel_rd32,
-	.wr32 = _nvkm_fifo_channel_wr32,
-	.ntfy = _nvkm_fifo_channel_ntfy
-};
-
-struct nvkm_oclass
-nv04_fifo_sclass[] = {
-	{ NV03_CHANNEL_DMA, &nv04_fifo_ofuncs },
-	{}
-};
-
-int
-nv04_fifo_context_ctor(struct nvkm_object *parent,
-		       struct nvkm_object *engine,
-		       struct nvkm_oclass *oclass, void *data, u32 size,
-		       struct nvkm_object **pobject)
-{
-	struct nv04_fifo_base *base;
-	int ret;
-
-	ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
-				       0x1000, NVOBJ_FLAG_HEAP, &base);
-	*pobject = nv_object(base);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-struct nvkm_oclass
-nv04_fifo_cclass = {
-	.handle = NV_ENGCTX(FIFO, 0x04),
-	.ofuncs = &(struct nvkm_ofuncs) {
-		.ctor = nv04_fifo_context_ctor,
-		.dtor = _nvkm_fifo_context_dtor,
-		.init = _nvkm_fifo_context_init,
-		.fini = _nvkm_fifo_context_fini,
-		.rd32 = _nvkm_fifo_context_rd32,
-		.wr32 = _nvkm_fifo_context_wr32,
-	},
+const struct nvkm_fifo_chan_oclass
+nv04_fifo_dma_oclass = {
+	.base.oclass = NV03_CHANNEL_DMA,
+	.base.minver = 0,
+	.base.maxver = 0,
+	.ctor = nv04_fifo_dma_new,
 };