diff options
Diffstat (limited to 'arch/sh/include/cpu-sh3')
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/dac.h | 12 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/dma-register.h | 41 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/dma.h | 23 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/ubc.h | 42 |
4 files changed, 47 insertions, 71 deletions
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h index 05fda8316ebc..98f1d15f0ab5 100644 --- a/arch/sh/include/cpu-sh3/cpu/dac.h +++ b/arch/sh/include/cpu-sh3/cpu/dac.h @@ -17,25 +17,25 @@ static __inline__ void sh_dac_enable(int channel) { unsigned char v; - v = ctrl_inb(DACR); + v = __raw_readb(DACR); if(channel) v |= DACR_DAOE1; else v |= DACR_DAOE0; - ctrl_outb(v,DACR); + __raw_writeb(v,DACR); } static __inline__ void sh_dac_disable(int channel) { unsigned char v; - v = ctrl_inb(DACR); + v = __raw_readb(DACR); if(channel) v &= ~DACR_DAOE1; else v &= ~DACR_DAOE0; - ctrl_outb(v,DACR); + __raw_writeb(v,DACR); } static __inline__ void sh_dac_output(u8 value, int channel) { - if(channel) ctrl_outb(value,DADR1); - else ctrl_outb(value,DADR0); + if(channel) __raw_writeb(value,DADR1); + else __raw_writeb(value,DADR0); } #endif /* __ASM_CPU_SH3_DAC_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/dma-register.h b/arch/sh/include/cpu-sh3/cpu/dma-register.h new file mode 100644 index 000000000000..2349e488c9a6 --- /dev/null +++ b/arch/sh/include/cpu-sh3/cpu/dma-register.h @@ -0,0 +1,41 @@ +/* + * SH3 CPU-specific DMA definitions, used by both DMA drivers + * + * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef CPU_DMA_REGISTER_H +#define CPU_DMA_REGISTER_H + +#define CHCR_TS_LOW_MASK 0x18 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 + +#define DMAOR_INIT DMAOR_DME + +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + */ +enum { + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_128BIT, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +#define TS_SHIFT { \ + [XMIT_SZ_8BIT] = 0, \ + [XMIT_SZ_16BIT] = 1, \ + [XMIT_SZ_32BIT] = 2, \ + [XMIT_SZ_128BIT] = 4, \ +} + +#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) + +#endif diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h index 0ea15f3f2363..24e28b91c9d5 100644 --- a/arch/sh/include/cpu-sh3/cpu/dma.h +++ b/arch/sh/include/cpu-sh3/cpu/dma.h @@ -20,27 +20,4 @@ #define TS_32 0x00000010 #define TS_128 0x00000018 -#define CHCR_TS_MASK 0x18 -#define CHCR_TS_SHIFT 3 - -#define DMAOR_INIT DMAOR_DME - -/* - * The SuperH DMAC supports a number of transmit sizes, we list them here, - * with their respective values as they appear in the CHCR registers. - */ -enum { - XMIT_SZ_8BIT, - XMIT_SZ_16BIT, - XMIT_SZ_32BIT, - XMIT_SZ_128BIT, -}; - -static unsigned int ts_shift[] __maybe_unused = { - [XMIT_SZ_8BIT] = 0, - [XMIT_SZ_16BIT] = 1, - [XMIT_SZ_32BIT] = 2, - [XMIT_SZ_128BIT] = 4, -}; - #endif /* __ASM_CPU_SH3_DMA_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/ubc.h b/arch/sh/include/cpu-sh3/cpu/ubc.h deleted file mode 100644 index 4e6381d5ff7a..000000000000 --- a/arch/sh/include/cpu-sh3/cpu/ubc.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-sh/cpu-sh3/ubc.h - * - * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH3_UBC_H -#define __ASM_CPU_SH3_UBC_H - -#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) -#define UBC_BARA 0xa4ffffb0 -#define UBC_BAMRA 0xa4ffffb4 -#define UBC_BBRA 0xa4ffffb8 -#define UBC_BASRA 0xffffffe4 -#define UBC_BARB 0xa4ffffa0 -#define UBC_BAMRB 0xa4ffffa4 -#define UBC_BBRB 0xa4ffffa8 -#define UBC_BASRB 0xffffffe8 -#define UBC_BDRB 0xa4ffff90 -#define UBC_BDMRB 0xa4ffff94 -#define UBC_BRCR 0xa4ffff98 -#else -#define UBC_BARA 0xffffffb0 -#define UBC_BAMRA 0xffffffb4 -#define UBC_BBRA 0xffffffb8 -#define UBC_BASRA 0xffffffe4 -#define UBC_BARB 0xffffffa0 -#define UBC_BAMRB 0xffffffa4 -#define UBC_BBRB 0xffffffa8 -#define UBC_BASRB 0xffffffe8 -#define UBC_BDRB 0xffffff90 -#define UBC_BDMRB 0xffffff94 -#define UBC_BRCR 0xffffff98 -#endif - -#endif /* __ASM_CPU_SH3_UBC_H */ |