diff options
Diffstat (limited to 'arch/mips/mti-malta/malta-int.c')
| -rw-r--r-- | arch/mips/mti-malta/malta-int.c | 93 |
1 files changed, 26 insertions, 67 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index ca3e3a46a42f..b71ee809191a 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -26,6 +26,7 @@ #include <asm/i8259.h> #include <asm/irq_cpu.h> #include <asm/irq_regs.h> +#include <asm/mips-cm.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> #include <asm/gt64120.h> @@ -33,13 +34,10 @@ #include <asm/mips-boards/msc01_pci.h> #include <asm/msc01_ic.h> #include <asm/gic.h> -#include <asm/gcmpregs.h> #include <asm/setup.h> #include <asm/rtlx.h> -int gcmp_present = -1; static unsigned long _msc01_biu_base; -static unsigned long _gcmp_base; static unsigned int ipi_map[NR_CPUS]; static DEFINE_RAW_SPINLOCK(mips_irq_lock); @@ -119,7 +117,7 @@ static void malta_hw0_irqdispatch(void) do_IRQ(MALTA_INT_BASE + irq); -#ifdef MIPS_VPE_APSP_API +#ifdef CONFIG_MIPS_VPE_APSP_API_MT if (aprp_hook) aprp_hook(); #endif @@ -288,10 +286,6 @@ asmlinkage void plat_irq_dispatch(void) #ifdef CONFIG_MIPS_MT_SMP - -#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 -#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 - #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ #define C_RESCHED C_SW0 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ @@ -308,9 +302,16 @@ static void ipi_call_dispatch(void) do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); } +#endif /* CONFIG_MIPS_MT_SMP */ + +#ifdef CONFIG_MIPS_GIC_IPI + +#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 +#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 + static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) { -#ifdef MIPS_VPE_APSP_API +#ifdef CONFIG_MIPS_VPE_APSP_API_CMP if (aprp_hook) aprp_hook(); #endif @@ -338,7 +339,7 @@ static struct irqaction irq_call = { .flags = IRQF_PERCPU, .name = "IPI_call" }; -#endif /* CONFIG_MIPS_MT_SMP */ +#endif /* CONFIG_MIPS_GIC_IPI */ static int gic_resched_int_base; static int gic_call_int_base; @@ -418,49 +419,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { }; #undef X -/* - * GCMP needs to be detected before any SMP initialisation - */ -int __init gcmp_probe(unsigned long addr, unsigned long size) -{ - if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) && - (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) { - gcmp_present = 0; - pr_debug("GCMP NOT present\n"); - return gcmp_present; - } - - if (gcmp_present >= 0) - return gcmp_present; - - _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, - GCMP_ADDRSPACE_SZ); - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, - MSC01_BIU_ADDRSPACE_SZ); - gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == - GCMP_BASE_ADDR); - - if (gcmp_present) - pr_debug("GCMP present\n"); - return gcmp_present; -} - -/* Return the number of IOCU's present */ -int __init gcmp_niocu(void) -{ - return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> - GCMP_GCB_GC_NUMIOCU_SHF) : 0; -} - -/* Set GCMP region attributes */ -void __init gcmp_setregion(int region, unsigned long base, - unsigned long mask, int type) -{ - GCMPGCBn(CMxBASE, region) = base; - GCMPGCBn(CMxMASK, region) = mask | type; -} - -#if defined(CONFIG_MIPS_MT_SMP) +#ifdef CONFIG_MIPS_GIC_IPI static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) { int intr = baseintr + cpu; @@ -496,8 +455,8 @@ void __init arch_init_irq(void) if (!cpu_has_veic) mips_cpu_irq_init(); - if (gcmp_present) { - GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; + if (mips_cm_present()) { + write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); gic_present = 1; } else { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { @@ -576,7 +535,7 @@ void __init arch_init_irq(void) if (gic_present) { /* FIXME */ int i; -#if defined(CONFIG_MIPS_MT_SMP) +#if defined(CONFIG_MIPS_GIC_IPI) gic_call_int_base = GIC_NUM_INTRS - (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids; gic_resched_int_base = gic_call_int_base - nr_cpu_ids; @@ -584,14 +543,14 @@ void __init arch_init_irq(void) #endif gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); - if (!gcmp_present) { + if (!mips_cm_present()) { /* Enable the GIC */ i = REG(_msc01_biu_base, MSC01_SC_CFG); REG(_msc01_biu_base, MSC01_SC_CFG) = (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); pr_debug("GIC Enabled\n"); } -#if defined(CONFIG_MIPS_MT_SMP) +#if defined(CONFIG_MIPS_GIC_IPI) /* set up ipi interrupts */ if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); @@ -708,16 +667,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) /* This duplicates the handling in do_be which seems wrong */ int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; - if (gcmp_present) { - unsigned long cm_error = GCMPGCB(GCMEC); - unsigned long cm_addr = GCMPGCB(GCMEA); - unsigned long cm_other = GCMPGCB(GCMEO); + if (mips_cm_present()) { + unsigned long cm_error = read_gcr_error_cause(); + unsigned long cm_addr = read_gcr_error_addr(); + unsigned long cm_other = read_gcr_error_mult(); unsigned long cause, ocause; char buf[256]; - cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); + cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK; if (cause != 0) { - cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; + cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF; if (cause < 16) { unsigned long cca_bits = (cm_error >> 15) & 7; unsigned long tr_bits = (cm_error >> 12) & 7; @@ -748,8 +707,8 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) mcmd[cmd_bits], sport_bits); } - ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> - GCMP_GCB_GMEO_ERROR_2ND_SHF; + ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >> + CM_GCR_ERROR_MULT_ERR2ND_SHF; pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error, causes[cause], buf); @@ -757,7 +716,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); /* reprime cause register */ - GCMPGCB(GCMEC) = 0; + write_gcr_error_cause(0); } } |