diff options
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/Kconfig | 16 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/boards/cm_bf561.c | 11 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/boards/ezkit.c | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/coreb.c | 396 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 104 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/blackfin.h | 1 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 29 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 56 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/mem_map.h | 58 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/smp.c | 4 |
10 files changed, 235 insertions, 446 deletions
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig index 638ec38ca470..cb9743641511 100644 --- a/arch/blackfin/mach-bf561/Kconfig +++ b/arch/blackfin/mach-bf561/Kconfig @@ -9,22 +9,9 @@ if (!SMP) comment "Core B Support" config BF561_COREB - bool "Enable Core B support" + bool "Enable Core B loader" default y -config BF561_COREB_RESET - bool "Enable Core B reset support" - default n - help - This requires code in the application that is loaded - into Core B. In order to reset, the application needs - to install an interrupt handler for Supplemental - Interrupt 0, that sets RETI to 0xff600000 and writes - bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. - This causes Core B to stall when Supplemental Interrupt - 0 is set, and will reset PC to 0xff600000 when - COREB_SRAM_INIT is cleared. - endif comment "Interrupt Priority Assignment" @@ -138,6 +125,7 @@ config IRQ_DMA2_11 default 9 config IRQ_TIMER0 int "TIMER 0 Interrupt" + default 7 if TICKSOURCE_GPTMR0 default 8 config IRQ_TIMER1 int "TIMER 1 Interrupt" diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index f623c6b0719f..0c9d72c5f5ba 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -83,7 +83,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { }; #endif -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) +#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) /* SPI ADC chip */ static struct bfin5xx_spi_chip spi_adc_chip_info = { .enable_dma = 1, /* use dma transfer with this chip*/ @@ -126,7 +126,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) +#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) { .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ @@ -177,8 +177,13 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, - } + }, }; /* SPI controller data */ diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 0e2178a1aec5..4df904f9e90a 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, @@ -304,6 +303,11 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, } }; diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index 8598098c0840..93635a766f9c 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -1,406 +1,74 @@ -/* - * File: arch/blackfin/mach-bf561/coreb.c - * Based on: - * Author: +/* Load firmware into Core B on a BF561 * - * Created: - * Description: Handle CoreB on a BF561 - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* The Core B reset func requires code in the application that is loaded into + * Core B. In order to reset, the application needs to install an interrupt + * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and + * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core + * B to stall when Supplemental Interrupt 0 is set, and will reset PC to + * 0xff600000 when COREB_SRAM_INIT is cleared. */ -#include <linux/mm.h> -#include <linux/miscdevice.h> #include <linux/device.h> -#include <linux/ioport.h> -#include <linux/module.h> -#include <linux/uaccess.h> #include <linux/fs.h> -#include <asm/dma.h> -#include <asm/cacheflush.h> - -#define MODULE_VER "v0.1" - -static spinlock_t coreb_lock; -static wait_queue_head_t coreb_dma_wait; - -#define COREB_IS_OPEN 0x00000001 -#define COREB_IS_RUNNING 0x00000010 +#include <linux/kernel.h> +#include <linux/miscdevice.h> +#include <linux/module.h> -#define CMD_COREB_INDEX 1 #define CMD_COREB_START 2 #define CMD_COREB_STOP 3 #define CMD_COREB_RESET 4 -#define COREB_MINOR 229 - -static unsigned long coreb_status = 0; -static unsigned long coreb_base = 0xff600000; -static unsigned long coreb_size = 0x4000; -int coreb_dma_done; - -static loff_t coreb_lseek(struct file *file, loff_t offset, int origin); -static ssize_t coreb_read(struct file *file, char *buf, size_t count, - loff_t * ppos); -static ssize_t coreb_write(struct file *file, const char *buf, size_t count, - loff_t * ppos); -static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg); -static int coreb_open(struct inode *inode, struct file *file); -static int coreb_release(struct inode *inode, struct file *file); - -static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id) -{ - clear_dma_irqstat(CH_MEM_STREAM2_DEST); - coreb_dma_done = 1; - wake_up_interruptible(&coreb_dma_wait); - return IRQ_HANDLED; -} - -static ssize_t coreb_write(struct file *file, const char *buf, size_t count, - loff_t * ppos) -{ - unsigned long p = *ppos; - ssize_t wrote = 0; - - if (p + count > coreb_size) - return -EFAULT; - - while (count > 0) { - int len = count; - - if (len > PAGE_SIZE) - len = PAGE_SIZE; - - coreb_dma_done = 0; - - flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); - /* Source Channel */ - set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf); - set_dma_x_count(CH_MEM_STREAM2_SRC, len); - set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_SRC, 0); - /* Destination Channel */ - set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p); - set_dma_x_count(CH_MEM_STREAM2_DEST, len); - set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN); - - enable_dma(CH_MEM_STREAM2_SRC); - enable_dma(CH_MEM_STREAM2_DEST); - - wait_event_interruptible(coreb_dma_wait, coreb_dma_done); - - disable_dma(CH_MEM_STREAM2_SRC); - disable_dma(CH_MEM_STREAM2_DEST); - - count -= len; - wrote += len; - buf += len; - p += len; - } - *ppos = p; - return wrote; -} - -static ssize_t coreb_read(struct file *file, char *buf, size_t count, - loff_t * ppos) -{ - unsigned long p = *ppos; - ssize_t read = 0; - - if ((p + count) > coreb_size) - return -EFAULT; - - while (count > 0) { - int len = count; - - if (len > PAGE_SIZE) - len = PAGE_SIZE; - - coreb_dma_done = 0; - - invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); - /* Source Channel */ - set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p); - set_dma_x_count(CH_MEM_STREAM2_SRC, len); - set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_SRC, 0); - /* Destination Channel */ - set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf); - set_dma_x_count(CH_MEM_STREAM2_DEST, len); - set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN); - - enable_dma(CH_MEM_STREAM2_SRC); - enable_dma(CH_MEM_STREAM2_DEST); - - wait_event_interruptible(coreb_dma_wait, coreb_dma_done); - - disable_dma(CH_MEM_STREAM2_SRC); - disable_dma(CH_MEM_STREAM2_DEST); - - count -= len; - read += len; - buf += len; - p += len; - } - - return read; -} - -static loff_t coreb_lseek(struct file *file, loff_t offset, int origin) +static int +coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { - loff_t ret; - - mutex_lock(&file->f_dentry->d_inode->i_mutex); - - switch (origin) { - case 0 /* SEEK_SET */ : - if (offset < coreb_size) { - file->f_pos = offset; - ret = file->f_pos; - } else - ret = -EINVAL; - break; - case 1 /* SEEK_CUR */ : - if ((offset + file->f_pos) < coreb_size) { - file->f_pos += offset; - ret = file->f_pos; - } else - ret = -EINVAL; - default: - ret = -EINVAL; - } - mutex_unlock(&file->f_dentry->d_inode->i_mutex); - return ret; -} - -/* No BKL needed here */ -static int coreb_open(struct inode *inode, struct file *file) -{ - spin_lock_irq(&coreb_lock); - - if (coreb_status & COREB_IS_OPEN) - goto out_busy; - - coreb_status |= COREB_IS_OPEN; - - spin_unlock_irq(&coreb_lock); - return 0; - - out_busy: - spin_unlock_irq(&coreb_lock); - return -EBUSY; -} - -static int coreb_release(struct inode *inode, struct file *file) -{ - spin_lock_irq(&coreb_lock); - coreb_status &= ~COREB_IS_OPEN; - spin_unlock_irq(&coreb_lock); - return 0; -} - -static int coreb_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - int retval = 0; - int coreb_index = 0; + int ret = 0; switch (cmd) { - case CMD_COREB_INDEX: - if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) { - retval = -EFAULT; - break; - } - - spin_lock_irq(&coreb_lock); - switch (coreb_index) { - case 0: - coreb_base = 0xff600000; - coreb_size = 0x4000; - break; - case 1: - coreb_base = 0xff610000; - coreb_size = 0x4000; - break; - case 2: - coreb_base = 0xff500000; - coreb_size = 0x8000; - break; - case 3: - coreb_base = 0xff400000; - coreb_size = 0x8000; - break; - default: - retval = -EINVAL; - break; - } - spin_unlock_irq(&coreb_lock); - - mutex_lock(&file->f_dentry->d_inode->i_mutex); - file->f_pos = 0; - mutex_unlock(&file->f_dentry->d_inode->i_mutex); - break; case CMD_COREB_START: - spin_lock_irq(&coreb_lock); - if (coreb_status & COREB_IS_RUNNING) { - retval = -EBUSY; - break; - } - printk(KERN_INFO "Starting Core B\n"); - coreb_status |= COREB_IS_RUNNING; bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); - SSYNC(); - spin_unlock_irq(&coreb_lock); break; -#if defined(CONFIG_BF561_COREB_RESET) case CMD_COREB_STOP: - spin_lock_irq(&coreb_lock); - printk(KERN_INFO "Stopping Core B\n"); bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); - coreb_status &= ~COREB_IS_RUNNING; - spin_unlock_irq(&coreb_lock); break; case CMD_COREB_RESET: - printk(KERN_INFO "Resetting Core B\n"); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); break; -#endif + default: + ret = -EINVAL; + break; } - return retval; + CSYNC(); + + return ret; } static struct file_operations coreb_fops = { - .owner = THIS_MODULE, - .llseek = coreb_lseek, - .read = coreb_read, - .write = coreb_write, - .ioctl = coreb_ioctl, - .open = coreb_open, - .release = coreb_release + .owner = THIS_MODULE, + .ioctl = coreb_ioctl, }; static struct miscdevice coreb_dev = { - COREB_MINOR, - "coreb", - &coreb_fops + .minor = MISC_DYNAMIC_MINOR, + .name = "coreb", + .fops = &coreb_fops, }; -static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf) +static int __init bf561_coreb_init(void) { - return sprintf(buf, - "Base Address:\t0x%08lx\n" - "Core B is %s\n" - "SICA_SYSCR:\t%04x\n" - "SICB_SYSCR:\t%04x\n" - "\n" - "IRQ Status:\tCore A\t\tCore B\n" - "ISR0:\t\t%08x\t\t%08x\n" - "ISR1:\t\t%08x\t\t%08x\n" - "IMASK0:\t\t%08x\t\t%08x\n" - "IMASK1:\t\t%08x\t\t%08x\n", - coreb_base, - coreb_status & COREB_IS_RUNNING ? "running" : "stalled", - bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(), - bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(), - bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(), - bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(), - bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1()); -} - -static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL); - -int __init bf561_coreb_init(void) -{ - init_waitqueue_head(&coreb_dma_wait); - - spin_lock_init(&coreb_lock); - /* Request the core memory regions for Core B */ - if (request_mem_region(0xff600000, 0x4000, - "Core B - Instruction SRAM") == NULL) - goto exit; - - if (request_mem_region(0xFF610000, 0x4000, - "Core B - Instruction SRAM") == NULL) - goto release_instruction_a_sram; - - if (request_mem_region(0xFF500000, 0x8000, - "Core B - Data Bank B SRAM") == NULL) - goto release_instruction_b_sram; - - if (request_mem_region(0xff400000, 0x8000, - "Core B - Data Bank A SRAM") == NULL) - goto release_data_b_sram; - - if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0) - goto release_data_a_sram; - - if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0) - goto release_dma_dest; - - set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL); - - misc_register(&coreb_dev); - - if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status)) - goto release_dma_src; - - printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER); - return 0; - - release_dma_src: - free_dma(CH_MEM_STREAM2_SRC); - release_dma_dest: - free_dma(CH_MEM_STREAM2_DEST); - release_data_a_sram: - release_mem_region(0xff400000, 0x8000); - release_data_b_sram: - release_mem_region(0xff500000, 0x8000); - release_instruction_b_sram: - release_mem_region(0xff610000, 0x4000); - release_instruction_a_sram: - release_mem_region(0xff600000, 0x4000); - exit: - return -ENOMEM; + return misc_register(&coreb_dev); } +module_init(bf561_coreb_init); -void __exit bf561_coreb_exit(void) +static void __exit bf561_coreb_exit(void) { - device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status); misc_deregister(&coreb_dev); - - release_mem_region(0xff610000, 0x4000); - release_mem_region(0xff600000, 0x4000); - release_mem_region(0xff500000, 0x8000); - release_mem_region(0xff400000, 0x8000); - - free_dma(CH_MEM_STREAM2_DEST); - free_dma(CH_MEM_STREAM2_SRC); } - -module_init(bf561_coreb_init); module_exit(bf561_coreb_exit); MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index d0b0b3506440..94b8e277f09d 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List */ @@ -18,19 +18,19 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) @@ -52,7 +52,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) /* DMA engine may lose data due to incorrect handshaking */ #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) @@ -66,7 +66,7 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) @@ -76,17 +76,17 @@ #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) /* DMEM_CONTROL<12> is not set on Reset */ #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) -/* Turning Serial Ports on with External Frame Syncs */ +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) /* DSPID register values incorrect */ #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) @@ -96,29 +96,29 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) @@ -126,7 +126,7 @@ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +134,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -158,15 +158,15 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -192,9 +192,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,27 +202,27 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) -/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +230,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -276,18 +276,30 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000119 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) #endif diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index f79f6626b7ec..8be31358ef88 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -34,7 +34,6 @@ #define BF561_FAMILY #include "bf561.h" -#include "mem_map.h" #include "defBF561.h" #include "anomaly.h" diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index 95d609f11c97..9d9858c2be68 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h @@ -1526,6 +1526,35 @@ #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG() +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS() +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY() +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY() +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT() +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT() +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR() +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG() +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS() +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY() +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY() +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT() +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT() +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR() +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val) + /* These need to be last due to the cdef/linux inter-dependencies */ #include <asm/irq.h> diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index cf922295f4ce..5fc0f05026e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -796,6 +796,62 @@ #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ +#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR +#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR +#define MDMA_D0_CONFIG MDMA1_D0_CONFIG +#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT +#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY +#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT +#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY +#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR +#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR +#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS +#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP +#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT +#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT + +#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR +#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR +#define MDMA_S0_CONFIG MDMA1_S0_CONFIG +#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT +#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY +#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT +#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY +#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR +#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR +#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS +#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP +#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT +#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT + +#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR +#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR +#define MDMA_D1_CONFIG MDMA1_D1_CONFIG +#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT +#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY +#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT +#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY +#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR +#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR +#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS +#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP +#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT +#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT + +#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR +#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR +#define MDMA_S1_CONFIG MDMA1_S1_CONFIG +#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT +#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY +#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT +#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY +#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR +#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR +#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS +#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP +#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT +#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT + /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index 419dffdc96eb..a63e15c86d90 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -1,13 +1,16 @@ /* - * Memory MAP - * Common header file for blackfin BF561 of processors. + * BF561 memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_561_H_ -#define _MEM_MAP_561_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -82,9 +85,6 @@ #define COREA_L1_SCRATCH_START 0xFFB00000 #define COREB_L1_SCRATCH_START 0xFF700000 -#define L1_SCRATCH_START COREA_L1_SCRATCH_START -#define L1_SCRATCH_LENGTH 0x1000 - #ifdef __ASSEMBLY__ /* @@ -155,14 +155,42 @@ dreg = ROT dreg BY -1; \ dreg = CC; -#else -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; +static inline unsigned long get_l1_scratch_start_cpu(int cpu) +{ + return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; +} +static inline unsigned long get_l1_code_start_cpu(int cpu) +{ + return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; +} +static inline unsigned long get_l1_data_a_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; +} +static inline unsigned long get_l1_data_b_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; +} + +static inline unsigned long get_l1_scratch_start(void) +{ + return get_l1_scratch_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_code_start(void) +{ + return get_l1_code_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_a_start(void) +{ + return get_l1_data_a_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_b_start(void) +{ + return get_l1_data_b_start_cpu(blackfin_core_id()); +} -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) #endif /* CONFIG_SMP */ #endif /* __ASSEMBLY__ */ -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 9b27e698c0b2..8c10701c251f 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -133,9 +133,9 @@ void __init platform_request_ipi(irq_handler_t handler) int ret; ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, - "SMP interrupt", handler); + "Supplemental Interrupt0", handler); if (ret) - panic("Cannot request supplemental interrupt 0 for IPI service\n"); + panic("Cannot request supplemental interrupt 0 for IPI service"); } void platform_send_ipi(cpumask_t callmap) |