diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/anomaly.h | 43 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/blackfin.h | 90 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/mem_map.h | 51 |
3 files changed, 45 insertions, 139 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index c510ae688e28..52b116ae522a 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -7,7 +7,7 @@ */ /* This file should be up to date with: - * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -18,7 +18,7 @@ # error will not work on BF548 silicon version 0.0, or 0.1 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) @@ -30,17 +30,17 @@ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ +/* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) @@ -162,6 +162,8 @@ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) /* OTP Write Accesses Not Supported */ #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ @@ -176,10 +178,28 @@ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) /* USB DMA Mode 1 Short Packet Data Corruption */ #define ANOMALY_05000450 (1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ -#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) -/* False Hardware Error when RETI points to invalid memory */ +#define ANOMALY_05000456 (1) +/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ +#define ANOMALY_05000457 (1) +/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ +#define ANOMALY_05000460 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* USB DMA RX Data Corruption */ +#define ANOMALY_05000463 (1) +/* USB TX DMA Hang */ +#define ANOMALY_05000464 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ +#define ANOMALY_05000466 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -189,35 +209,44 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) #define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) #define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) #define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000248 (0) #define ANOMALY_05000250 (0) #define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000287 (0) #define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index cf6c1500222a..318667b2f036 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -33,7 +33,6 @@ #define _MACH_BLACKFIN_H_ #include "bf548.h" -#include "mem_map.h" #include "anomaly.h" #ifdef CONFIG_BF542 @@ -73,97 +72,8 @@ #include "cdefBF549.h" #endif -/* UART 1*/ -#define bfin_read_UART_THR() bfin_read_UART1_THR() -#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) -#define bfin_read_UART_RBR() bfin_read_UART1_RBR() -#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) -#define bfin_read_UART_DLL() bfin_read_UART1_DLL() -#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) -#define bfin_read_UART_IER() bfin_read_UART1_IER() -#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) -#define bfin_read_UART_DLH() bfin_read_UART1_DLH() -#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) -#define bfin_read_UART_IIR() bfin_read_UART1_IIR() -#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) -#define bfin_read_UART_LCR() bfin_read_UART1_LCR() -#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) -#define bfin_read_UART_MCR() bfin_read_UART1_MCR() -#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) -#define bfin_read_UART_LSR() bfin_read_UART1_LSR() -#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) -#define bfin_read_UART_SCR() bfin_read_UART1_SCR() -#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) -#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() -#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) - #endif -/* MAP used DEFINES from BF533 to BF54x - so we don't need to change - * them in the driver, kernel, etc. */ - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 - -/* UART 0*/ - -/* DMA Channel */ -#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() -#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) -#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() -#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) -#define CH_UART_RX CH_UART1_RX -#define CH_UART_TX CH_UART1_TX - -/* System Interrupt Controller */ -#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() -#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) -#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() -#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) -#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() -#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) -#define IRQ_UART_RX IRQ_UART1_RX -#define IRQ_UART_TX IRQ_UART1_TX -#define IRQ_UART_ERROR IRQ_UART1_ERROR - -/* MMR Registers*/ -#define bfin_read_UART_THR() bfin_read_UART1_THR() -#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) -#define bfin_read_UART_RBR() bfin_read_UART1_RBR() -#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) -#define bfin_read_UART_DLL() bfin_read_UART1_DLL() -#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) -#define bfin_read_UART_IER() bfin_read_UART1_IER() -#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) -#define bfin_read_UART_DLH() bfin_read_UART1_DLH() -#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) -#define bfin_read_UART_IIR() bfin_read_UART1_IIR() -#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) -#define bfin_read_UART_LCR() bfin_read_UART1_LCR() -#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) -#define bfin_read_UART_MCR() bfin_read_UART1_MCR() -#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) -#define bfin_read_UART_LSR() bfin_read_UART1_LSR() -#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) -#define bfin_read_UART_SCR() bfin_read_UART1_SCR() -#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) -#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() -#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) - -#define BFIN_UART_THR UART1_THR -#define BFIN_UART_RBR UART1_RBR -#define BFIN_UART_DLL UART1_DLL -#define BFIN_UART_IER UART1_IER -#define BFIN_UART_DLH UART1_DLH -#define BFIN_UART_IIR UART1_IIR -#define BFIN_UART_LCR UART1_LCR -#define BFIN_UART_MCR UART1_MCR -#define BFIN_UART_LSR UART1_LSR -#define BFIN_UART_SCR UART1_SCR -#define BFIN_UART_GCTL UART1_GCTL - #define BFIN_UART_NR_PORTS 4 #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h index 70b9c1194024..caac2dfb41eb 100644 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf548/mem_map.h - * based on: - * author: + * BF548 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_548_H_ -#define _MEM_MAP_548_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -103,15 +81,4 @@ # define L2_LENGTH 0x20000 #endif -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif/* _MEM_MAP_548_H_ */ +#endif |