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-rw-r--r--arch/arm/mach-exynos4/Kconfig38
-rw-r--r--arch/arm/mach-exynos4/Makefile2
-rw-r--r--arch/arm/mach-exynos4/clock.c204
-rw-r--r--arch/arm/mach-exynos4/cpu.c2
-rw-r--r--arch/arm/mach-exynos4/dma.c1
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h8
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/pwm-clock.h70
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h74
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c34
-rw-r--r--arch/arm/mach-exynos4/mach-origen.c577
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c49
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c307
-rw-r--r--arch/arm/mach-exynos4/pm.c7
-rw-r--r--arch/arm/mach-exynos4/pmu.c353
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci.c47
-rw-r--r--arch/arm/mach-exynos4/sleep.S54
20 files changed, 1504 insertions, 353 deletions
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 44013e0672fe..59299ea5b2ff 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -13,11 +13,16 @@ config CPU_EXYNOS4210
bool
select SAMSUNG_DMADEV
select ARM_CPU_SUSPEND if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
help
Enable EXYNOS4210 CPU support
config SOC_EXYNOS4212
bool
+ select ARM_CPU_SUSPEND if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
help
Enable EXYNOS4212 SoC support
@@ -137,6 +142,14 @@ config MACH_SMDKV310
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
+ select S5P_DEV_FIMC0
+ select S5P_DEV_FIMC1
+ select S5P_DEV_FIMC2
+ select S5P_DEV_FIMC3
+ select S5P_DEV_I2C_HDMIPHY
+ select S5P_DEV_MFC
+ select S5P_DEV_TV
+ select S5P_DEV_USB_EHCI
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
@@ -151,6 +164,7 @@ config MACH_SMDKV310
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for Samsung SMDKV310
@@ -176,19 +190,26 @@ config MACH_UNIVERSAL_C210
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
+ select S5P_DEV_CSIS0
+ select S5P_DEV_FIMD0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
+ select S5P_DEV_I2C_HDMIPHY
select S5P_DEV_MFC
select S5P_DEV_ONENAND
+ select S5P_DEV_TV
select EXYNOS4_DEV_PD
+ select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
+ select EXYNOS4_SETUP_FIMC
+ select S5P_SETUP_MIPIPHY
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board.
@@ -197,6 +218,8 @@ config MACH_NURI
bool "Mobile NURI Board"
select CPU_EXYNOS4210
select S3C_DEV_WDT
+ select S3C_DEV_RTC
+ select S5P_DEV_FIMD0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
@@ -206,6 +229,7 @@ config MACH_NURI
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
+ select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
@@ -221,8 +245,22 @@ config MACH_ORIGEN
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
+ select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
+ select S5P_DEV_FIMC0
+ select S5P_DEV_FIMC1
+ select S5P_DEV_FIMC2
+ select S5P_DEV_FIMC3
+ select S5P_DEV_FIMD0
+ select S5P_DEV_I2C_HDMIPHY
+ select S5P_DEV_TV
+ select S5P_DEV_USB_EHCI
+ select EXYNOS4_DEV_PD
+ select SAMSUNG_DEV_BACKLIGHT
+ select SAMSUNG_DEV_PWM
+ select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_SDHCI
+ select EXYNOS4_SETUP_USB_PHY
help
Machine support for ORIGEN based on Samsung EXYNOS4210
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index c9b2e1f97e44..2bb18f431db9 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index a52024e309b0..2894f0adef5c 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -151,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
}
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+}
+
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -191,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
}
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -508,13 +523,43 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
+ .name = "dac",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "mixer",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "vp",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "hdmiphy",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_hdmiphy_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "dacphy",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_dac_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "dma",
- .devname = "s3c-pl330.0",
+ .devname = "dma-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dma",
- .devname = "s3c-pl330.1",
+ .devname = "dma-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
@@ -635,6 +680,12 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
+ .name = "i2c",
+ .devname = "s3c2440-hdmiphy-i2c",
+ .parent = &clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
.name = "SYSMMU_MDMA",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5),
@@ -836,6 +887,81 @@ static struct clksrc_sources clkset_mout_mfc = {
.nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
};
+static struct clk *clkset_sclk_dac_list[] = {
+ [0] = &clk_sclk_vpll.clk,
+ [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+ .sources = clkset_sclk_dac_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+ .clk = {
+ .name = "sclk_dac",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_sclk_dac,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .parent = &clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_hdmi_list[] = {
+ [0] = &clk_sclk_pixel.clk,
+ [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+ .sources = clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_sclk_hdmi,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_mixer_list[] = {
+ [0] = &clk_sclk_dac.clk,
+ [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+ .sources = clkset_sclk_mixer_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk clk_sclk_mixer = {
+ .clk = {
+ .name = "sclk_mixer",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_sclk_mixer,
+ .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+ &clk_sclk_dac,
+ &clk_sclk_pixel,
+ &clk_sclk_hdmi,
+ &clk_sclk_mixer,
+};
+
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
@@ -1162,6 +1288,71 @@ static struct clk_ops exynos4_fout_apll_ops = {
.get_rate = exynos4_fout_apll_get_rate,
};
+static u32 vpll_div[][8] = {
+ { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
+ { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int vpll_con0, vpll_con1 = 0;
+ unsigned int i;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ vpll_con0 = __raw_readl(S5P_VPLL_CON0);
+ vpll_con0 &= ~(0x1 << 27 | \
+ PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
+ PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+ PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ vpll_con1 = __raw_readl(S5P_VPLL_CON1);
+ vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
+ PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+ PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
+ if (vpll_div[i][0] == rate) {
+ vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+ vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+ vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+ vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+ vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+ vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+ vpll_con0 |= vpll_div[i][7] << 27;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(vpll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ __raw_writel(vpll_con0, S5P_VPLL_CON0);
+ __raw_writel(vpll_con1, S5P_VPLL_CON1);
+
+ /* Wait for VPLL lock */
+ while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+ continue;
+
+ clk->rate = rate;
+ return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+ .get_rate = exynos4_vpll_get_rate,
+ .set_rate = exynos4_vpll_set_rate,
+};
+
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
@@ -1219,6 +1410,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
+ clk_fout_vpll.ops = &exynos4_vpll_ops;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1246,7 +1438,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
}
static struct clk *clks[] __initdata = {
- /* Nothing here yet */
+ &clk_sclk_hdmi27m,
+ &clk_sclk_hdmiphy,
+ &clk_sclk_usbphy0,
+ &clk_sclk_usbphy1,
};
#ifdef CONFIG_PM_SLEEP
@@ -1280,6 +1475,9 @@ void __init exynos4_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
+ s3c_register_clksrc(sclk_tv[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index a348434f17b5..5b1765b37f75 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -28,6 +28,7 @@
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/reset.h>
+#include <plat/tv-core.h>
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
@@ -182,6 +183,7 @@ void __init exynos4_map_io(void)
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
+ s5p_hdmi_setname("exynos4-hdmi");
}
void __init exynos4_init_clocks(int xtal)
diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c
index d57d66255021..9667c61e64fb 100644
--- a/arch/arm/mach-exynos4/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -243,6 +243,7 @@ struct amba_device exynos4_device_pdma1 = {
static int __init exynos4_dma_init(void)
{
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+ amba_device_register(&exynos4_device_pdma1, &iomem_resource);
return 0;
}
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-exynos4/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 2d3f6bcd9bc0..dfd4b7eecb90 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -95,7 +95,11 @@
#define IRQ_2D IRQ_SPI(89)
#define IRQ_PCIE IRQ_SPI(90)
+#define IRQ_MIXER IRQ_SPI(91)
+#define IRQ_HDMI IRQ_SPI(92)
+#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
#define IRQ_MFC IRQ_SPI(94)
+#define IRQ_SDO IRQ_SPI(95)
#define IRQ_AUDIO_SS IRQ_SPI(96)
#define IRQ_I2S0 IRQ_SPI(97)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 9f97eb8499ee..918a979181af 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -112,6 +112,12 @@
#define EXYNOS4_PA_UART 0x13800000
+#define EXYNOS4_PA_VP 0x12C00000
+#define EXYNOS4_PA_MIXER 0x12C10000
+#define EXYNOS4_PA_SDO 0x12C20000
+#define EXYNOS4_PA_HDMI 0x12D00000
+#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
+
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
@@ -161,6 +167,12 @@
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
+#define S5P_PA_SDO EXYNOS4_PA_SDO
+#define S5P_PA_VP EXYNOS4_PA_VP
+#define S5P_PA_MIXER EXYNOS4_PA_MIXER
+#define S5P_PA_HDMI EXYNOS4_PA_HDMI
+#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
+
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
/* UART */
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index 1df3b81f96e8..9d8da51e35ca 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -14,6 +14,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+#ifndef __ASM_ARCH_PM_CORE_H
+#define __ASM_ARCH_PM_CORE_H __FILE__
+
#include <mach/regs-pmu.h>
static inline void s3c_pm_debug_init_uart(void)
@@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
/* nothing here yet */
}
-static inline void s3c_pm_saved_gpios(void)
+static inline void samsung_pm_saved_gpios(void)
{
/* nothing here yet */
}
+
+#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
index a952904b010e..632dd5630138 100644
--- a/arch/arm/mach-exynos4/include/mach/pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -13,6 +13,8 @@
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
+#define PMU_TABLE_END NULL
+
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
NUM_SYS_POWERDOWN,
};
+struct exynos4_pmu_conf {
+ void __iomem *reg;
+ unsigned int val[NUM_SYS_POWERDOWN];
+};
+
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pwm-clock.h b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
deleted file mode 100644
index 8e12090287bb..000000000000
--- a/arch/arm/mach-exynos4/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * EXYNOS4 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return tcfg == S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index cdf9b47c303c..4fff8e938fec 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -25,9 +25,10 @@
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFI1 (1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define S5P_USE_STANDBY_WFE1 (1 << 25)
-#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
+#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
#define S5P_SWRESET S5P_PMUREG(0x0400)
@@ -35,15 +36,17 @@
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
-#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE (1 << 0)
+#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE (1 << 0)
+
+#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
-#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
#define S5P_INFORM0 S5P_PMUREG(0x0800)
#define S5P_INFORM1 S5P_PMUREG(0x0804)
#define S5P_INFORM2 S5P_PMUREG(0x0808)
@@ -76,7 +79,6 @@
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
@@ -84,7 +86,6 @@
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
@@ -92,14 +93,11 @@
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
-#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
-#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
@@ -120,7 +118,6 @@
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
-#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
@@ -156,7 +153,6 @@
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
@@ -165,4 +161,60 @@
#define S5P_CHECK_SLEEP 0x00000BAD
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE (1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
+
#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 6e0536818bf5..2204911a24e9 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -32,10 +32,12 @@
#include <asm/mach-types.h>
#include <plat/adc.h>
+#include <plat/regs-fb-v4.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/ehci.h>
#include <plat/clock.h>
@@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = {
},
};
+/* Frame Buffer */
+static struct s3c_fb_pd_win nuri_fb_win0 = {
+ .win_mode = {
+ .left_margin = 64,
+ .right_margin = 16,
+ .upper_margin = 64,
+ .lower_margin = 1,
+ .hsync_len = 48,
+ .vsync_len = 3,
+ .xres = 1280,
+ .yres = 800,
+ .refresh = 60,
+ },
+ .max_bpp = 24,
+ .default_bpp = 16,
+ .virtual_x = 1280,
+ .virtual_y = 800,
+};
+
+static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
+ .win[0] = &nuri_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+ VIDCON0_CLKSEL_LCD,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
int gpio = EXYNOS4_GPE1(5);
@@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
&emmc_fixed_voltage,
+ &s5p_device_fimd0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
@@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = {
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
+ &exynos4_device_pd[PD_LCD0],
/* NURI Devices */
&nuri_gpio_keys,
@@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void)
i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
+ s5p_fimd0_set_platdata(&nuri_fb_pdata);
+
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+ s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
}
MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
index b5f6f38557c9..71db8480bb5a 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -14,16 +14,31 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/input.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8997.h>
+#include <linux/lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+#include <plat/pd.h>
+#include <plat/fb.h>
#include <mach/map.h>
@@ -72,19 +87,543 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
},
};
+static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
+ REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
+ REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
+ REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
+ REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
+};
+static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
+ REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
+ REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
+ REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
+ REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata buck1_consumer[] = {
+ REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck2_consumer[] = {
+ REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck3_consumer[] = {
+ REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
+};
+static struct regulator_consumer_supply __initdata buck7_consumer[] = {
+ REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+ .constraints = {
+ .name = "VDD_ABB_3.3V",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+ .constraints = {
+ .name = "VDD_ALIVE_1.1V",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+ .constraints = {
+ .name = "VMIPI_1.1V",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
+ .consumer_supplies = ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+ .constraints = {
+ .name = "VDD_RTC_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+ .constraints = {
+ .name = "VMIPI_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
+ .consumer_supplies = ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+ .constraints = {
+ .name = "VDD_AUD_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
+ .consumer_supplies = ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+ .constraints = {
+ .name = "VADC_3.3V",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
+ .consumer_supplies = ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+ .constraints = {
+ .name = "DVDD_SWB_2.8V",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
+ .consumer_supplies = ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+ .constraints = {
+ .name = "VDD_PLL_1.1V",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+ .constraints = {
+ .name = "VDD_AUD_3V",
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
+ .consumer_supplies = ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+ .constraints = {
+ .name = "AVDD18_SWB_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
+ .consumer_supplies = ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo17_data = {
+ .constraints = {
+ .name = "VDD_SWB_3.3V",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
+ .consumer_supplies = ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+ .constraints = {
+ .name = "VDD_MIF_1.2V",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+ .constraints = {
+ .name = "VDD_ARM_1.2V",
+ .min_uV = 950000,
+ .max_uV = 1350000,
+ .always_on = 1,
+ .boot_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
+ .consumer_supplies = buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+ .constraints = {
+ .name = "VDD_INT_1.1V",
+ .min_uV = 900000,
+ .max_uV = 1100000,
+ .always_on = 1,
+ .boot_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
+ .consumer_supplies = buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+ .constraints = {
+ .name = "VDD_G3D_1.1V",
+ .min_uV = 900000,
+ .max_uV = 1100000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
+ .consumer_supplies = buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+ .constraints = {
+ .name = "VDDQ_M1M2_1.2V",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+ .constraints = {
+ .name = "VDD_LCD_3.3V",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .boot_on = 1,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
+ .consumer_supplies = buck7_consumer,
+};
+
+static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
+ { MAX8997_LDO1, &max8997_ldo1_data },
+ { MAX8997_LDO2, &max8997_ldo2_data },
+ { MAX8997_LDO3, &max8997_ldo3_data },
+ { MAX8997_LDO4, &max8997_ldo4_data },
+ { MAX8997_LDO6, &max8997_ldo6_data },
+ { MAX8997_LDO7, &max8997_ldo7_data },
+ { MAX8997_LDO8, &max8997_ldo8_data },
+ { MAX8997_LDO9, &max8997_ldo9_data },
+ { MAX8997_LDO10, &max8997_ldo10_data },
+ { MAX8997_LDO11, &max8997_ldo11_data },
+ { MAX8997_LDO14, &max8997_ldo14_data },
+ { MAX8997_LDO17, &max8997_ldo17_data },
+ { MAX8997_LDO21, &max8997_ldo21_data },
+ { MAX8997_BUCK1, &max8997_buck1_data },
+ { MAX8997_BUCK2, &max8997_buck2_data },
+ { MAX8997_BUCK3, &max8997_buck3_data },
+ { MAX8997_BUCK5, &max8997_buck5_data },
+ { MAX8997_BUCK7, &max8997_buck7_data },
+};
+
+struct max8997_platform_data __initdata origen_max8997_pdata = {
+ .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
+ .regulators = origen_max8997_regulators,
+
+ .wakeup = true,
+ .buck1_gpiodvs = false,
+ .buck2_gpiodvs = false,
+ .buck5_gpiodvs = false,
+ .irq_base = IRQ_GPIO_END + 1,
+
+ .ignore_gpiodvs_side_effect = true,
+ .buck125_default_idx = 0x0,
+
+ .buck125_gpios[0] = EXYNOS4_GPX0(0),
+ .buck125_gpios[1] = EXYNOS4_GPX0(1),
+ .buck125_gpios[2] = EXYNOS4_GPX0(2),
+
+ .buck1_voltage[0] = 1350000,
+ .buck1_voltage[1] = 1300000,
+ .buck1_voltage[2] = 1250000,
+ .buck1_voltage[3] = 1200000,
+ .buck1_voltage[4] = 1150000,
+ .buck1_voltage[5] = 1100000,
+ .buck1_voltage[6] = 1000000,
+ .buck1_voltage[7] = 950000,
+
+ .buck2_voltage[0] = 1100000,
+ .buck2_voltage[1] = 1100000,
+ .buck2_voltage[2] = 1100000,
+ .buck2_voltage[3] = 1100000,
+ .buck2_voltage[4] = 1000000,
+ .buck2_voltage[5] = 1000000,
+ .buck2_voltage[6] = 1000000,
+ .buck2_voltage[7] = 1000000,
+
+ .buck5_voltage[0] = 1200000,
+ .buck5_voltage[1] = 1200000,
+ .buck5_voltage[2] = 1200000,
+ .buck5_voltage[3] = 1200000,
+ .buck5_voltage[4] = 1200000,
+ .buck5_voltage[5] = 1200000,
+ .buck5_voltage[6] = 1200000,
+ .buck5_voltage[7] = 1200000,
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("max8997", (0xCC >> 1)),
+ .platform_data = &origen_max8997_pdata,
+ .irq = IRQ_EINT(4),
+ },
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
- .cd_type = S3C_SDHCI_CD_GPIO,
- .ext_cd_gpio = EXYNOS4_GPK2(2),
- .ext_cd_gpio_invert = 1,
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+/* USB EHCI */
+static struct s5p_ehci_platdata origen_ehci_pdata;
+
+static void __init origen_ehci_init(void)
+{
+ struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
+
+ s5p_ehci_set_platdata(pdata);
+}
+
+static struct gpio_keys_button origen_gpio_keys_table[] = {
+ {
+ .code = KEY_MENU,
+ .gpio = EXYNOS4_GPX1(5),
+ .desc = "gpio-keys: KEY_MENU",
+ .type = EV_KEY,
+ .active_low = 1,
+ .wakeup = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_HOME,
+ .gpio = EXYNOS4_GPX1(6),
+ .desc = "gpio-keys: KEY_HOME",
+ .type = EV_KEY,
+ .active_low = 1,
+ .wakeup = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_BACK,
+ .gpio = EXYNOS4_GPX1(7),
+ .desc = "gpio-keys: KEY_BACK",
+ .type = EV_KEY,
+ .active_low = 1,
+ .wakeup = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_UP,
+ .gpio = EXYNOS4_GPX2(0),
+ .desc = "gpio-keys: KEY_UP",
+ .type = EV_KEY,
+ .active_low = 1,
+ .wakeup = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_DOWN,
+ .gpio = EXYNOS4_GPX2(1),
+ .desc = "gpio-keys: KEY_DOWN",
+ .type = EV_KEY,
+ .active_low = 1,
+ .wakeup = 1,
+ .debounce_interval = 1,
+ },
+};
+
+static struct gpio_keys_platform_data origen_gpio_keys_data = {
+ .buttons = origen_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
+};
+
+static struct platform_device origen_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &origen_gpio_keys_data,
+ },
+};
+
+static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+ int ret;
+
+ if (power)
+ ret = gpio_request_one(EXYNOS4_GPE3(4),
+ GPIOF_OUT_INIT_HIGH, "GPE3_4");
+ else
+ ret = gpio_request_one(EXYNOS4_GPE3(4),
+ GPIOF_OUT_INIT_LOW, "GPE3_4");
+
+ gpio_free(EXYNOS4_GPE3(4));
+
+ if (ret)
+ pr_err("failed to request gpio for LCD power: %d\n", ret);
+}
+
+static struct plat_lcd_data origen_lcd_hv070wsa_data = {
+ .set_power = lcd_hv070wsa_set_power,
+};
+
+static struct platform_device origen_lcd_hv070wsa = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &origen_lcd_hv070wsa_data,
+};
+
+static struct s3c_fb_pd_win origen_fb_win0 = {
+ .win_mode = {
+ .left_margin = 64,
+ .right_margin = 16,
+ .upper_margin = 64,
+ .lower_margin = 16,
+ .hsync_len = 48,
+ .vsync_len = 3,
+ .xres = 1024,
+ .yres = 600,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
+ .win[0] = &origen_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct platform_device *origen_devices[] __initdata = {
&s3c_device_hsmmc2,
+ &s3c_device_hsmmc0,
+ &s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_wdt,
+ &s5p_device_ehci,
+ &s5p_device_fimc0,
+ &s5p_device_fimc1,
+ &s5p_device_fimc2,
+ &s5p_device_fimc3,
+ &s5p_device_fimd0,
+ &s5p_device_hdmi,
+ &s5p_device_i2c_hdmiphy,
+ &s5p_device_mixer,
+ &exynos4_device_pd[PD_LCD0],
+ &exynos4_device_pd[PD_TV],
+ &origen_device_gpiokeys,
+ &origen_lcd_hv070wsa,
+};
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info origen_bl_gpio_info = {
+ .no = EXYNOS4_GPD0(0),
+ .func = S3C_GPIO_SFN(2),
};
+static struct platform_pwm_backlight_data origen_bl_data = {
+ .pwm_id = 0,
+ .pwm_period_ns = 1000,
+};
+
+static void s5p_tv_setup(void)
+{
+ /* Direct HPD to HDMI chip */
+ gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
+ s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+ s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+}
+
static void __init origen_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -92,10 +631,42 @@ static void __init origen_map_io(void)
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
}
+static void __init origen_power_init(void)
+{
+ gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
+ s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
+}
+
static void __init origen_machine_init(void)
{
+ origen_power_init();
+
+ s3c_i2c0_set_platdata(NULL);
+ i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+
+ /*
+ * Since sdhci instance 2 can contain a bootable media,
+ * sdhci instance 0 is registered after instance 2.
+ */
s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
+ s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
+
+ origen_ehci_init();
+ clk_xusbxti.rate = 24000000;
+
+ s5p_tv_setup();
+ s5p_i2c_hdmiphy_set_platdata(NULL);
+
+ s5p_fimd0_set_platdata(&origen_lcd_pdata);
+
platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+ s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+ s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+ s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+
+ samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
}
MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 2c1a076c6a73..cec2afabe7b4 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -37,6 +37,9 @@
#include <plat/pd.h>
#include <plat/gpio-cfg.h>
#include <plat/backlight.h>
+#include <plat/mfc.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
#include <mach/map.h>
@@ -232,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
{I2C_BOARD_INFO("wm8994", 0x1a),},
};
+/* USB EHCI */
+static struct s5p_ehci_platdata smdkv310_ehci_pdata;
+
+static void __init smdkv310_ehci_init(void)
+{
+ struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
+
+ s5p_ehci_set_platdata(pdata);
+}
+
static struct platform_device *smdkv310_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c1,
+ &s5p_device_i2c_hdmiphy,
&s3c_device_rtc,
&s3c_device_wdt,
+ &s5p_device_ehci,
+ &s5p_device_fimc0,
+ &s5p_device_fimc1,
+ &s5p_device_fimc2,
+ &s5p_device_fimc3,
&exynos4_device_ac97,
&exynos4_device_i2s0,
&samsung_device_keypad,
+ &s5p_device_mfc,
+ &s5p_device_mfc_l,
+ &s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_G3D],
&exynos4_device_pd[PD_LCD0],
@@ -258,6 +280,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&smdkv310_lcd_lte480wv,
&smdkv310_smsc911x,
&exynos4_device_ahci,
+ &s5p_device_hdmi,
+ &s5p_device_mixer,
};
static void __init smdkv310_smsc911x_init(void)
@@ -294,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
.pwm_period_ns = 1000,
};
+static void s5p_tv_setup(void)
+{
+ /* direct HPD to HDMI chip */
+ WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
+ s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+ s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+ /* setup dependencies between TV devices */
+ s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+ s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -301,6 +337,11 @@ static void __init smdkv310_map_io(void)
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}
+static void __init smdkv310_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
static void __init smdkv310_machine_init(void)
{
s3c_i2c1_set_platdata(NULL);
@@ -313,12 +354,19 @@ static void __init smdkv310_machine_init(void)
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+ s5p_tv_setup();
+ s5p_i2c_hdmiphy_set_platdata(NULL);
+
samsung_keypad_set_platdata(&smdkv310_keypad_data);
samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+ smdkv310_ehci_init();
+ clk_xusbxti.rate = 24000000;
+
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+ s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(SMDKV310, "SMDKV310")
@@ -329,6 +377,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
.map_io = smdkv310_map_io,
.init_machine = smdkv310_machine_init,
.timer = &exynos4_timer,
+ .reserve = &smdkv310_reserve,
MACHINE_END
MACHINE_START(SMDKC210, "SMDKC210")
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 2aac6f755c8e..a2a177ff4b44 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -13,6 +13,7 @@
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
+#include <linux/fb.h>
#include <linux/mfd/max8998.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
@@ -31,12 +32,21 @@
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
+#include <plat/fb.h>
#include <plat/mfc.h>
#include <plat/sdhci.h>
#include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
#include <mach/map.h>
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+#include <media/m5mols.h>
+
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
static struct regulator_consumer_supply lp3974_buck2_consumer =
REGULATOR_SUPPLY("vddg3d", NULL);
+static struct regulator_consumer_supply lp3974_buck3_consumer =
+ REGULATOR_SUPPLY("vdet", "s5p-sdo");
+
static struct regulator_init_data lp3974_buck1_data = {
.constraints = {
.name = "VINT_1.1V",
@@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
.enabled = 1,
},
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &lp3974_buck3_consumer,
};
static struct regulator_init_data lp3974_buck4_data = {
@@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
},
};
+static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
+ REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+ REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+ REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
+};
+
static struct regulator_init_data lp3974_ldo3_data = {
.constraints = {
.name = "VUSB+MIPI_1.1V",
@@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
+ .consumer_supplies = lp3974_ldo3_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
+ REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
};
static struct regulator_init_data lp3974_ldo4_data = {
@@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
+ .consumer_supplies = lp3974_ldo4_consumer,
};
static struct regulator_init_data lp3974_ldo5_data = {
@@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
},
};
+static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
+ REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
+};
+
static struct regulator_init_data lp3974_ldo7_data = {
.constraints = {
.name = "VLCD+VMIPI_1.8V",
@@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
+ .consumer_supplies = lp3974_ldo7_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
+ REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
};
static struct regulator_init_data lp3974_ldo8_data = {
@@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
+ .consumer_supplies = lp3974_ldo8_consumer,
};
static struct regulator_init_data lp3974_ldo9_data = {
@@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
},
};
+static struct regulator_consumer_supply lp3974_ldo11_consumer =
+ REGULATOR_SUPPLY("dig_28", "0-001f");
+
static struct regulator_init_data lp3974_ldo11_data = {
.constraints = {
.name = "CAM_AF_3.3V",
@@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &lp3974_ldo11_consumer,
};
static struct regulator_init_data lp3974_ldo12_data = {
@@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
},
};
+static struct regulator_consumer_supply lp3974_ldo14_consumer =
+ REGULATOR_SUPPLY("dig_18", "0-001f");
+
static struct regulator_init_data lp3974_ldo14_data = {
.constraints = {
.name = "CAM_I_HOST_1.8V",
@@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &lp3974_ldo14_consumer,
};
+
+static struct regulator_consumer_supply lp3974_ldo15_consumer =
+ REGULATOR_SUPPLY("dig_12", "0-001f");
+
static struct regulator_init_data lp3974_ldo15_data = {
.constraints = {
.name = "CAM_S_DIG+FM33_CORE_1.2V",
@@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &lp3974_ldo15_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+ REGULATOR_SUPPLY("a_sensor", "0-001f"),
};
static struct regulator_init_data lp3974_ldo16_data = {
@@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
.disabled = 1,
},
},
+ .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
+ .consumer_supplies = lp3974_ldo16_consumer,
};
static struct regulator_init_data lp3974_ldo17_data = {
@@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
.wakeup = true,
};
+
+enum fixed_regulator_id {
+ FIXED_REG_ID_MMC0,
+ FIXED_REG_ID_HDMI_5V,
+ FIXED_REG_ID_CAM_S_IF,
+ FIXED_REG_ID_CAM_I_CORE,
+ FIXED_REG_ID_CAM_VT_DIO,
+};
+
+static struct regulator_consumer_supply hdmi_fixed_consumer =
+ REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
+
+static struct regulator_init_data hdmi_fixed_voltage_init_data = {
+ .constraints = {
+ .name = "HDMI_5V",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &hdmi_fixed_consumer,
+};
+
+static struct fixed_voltage_config hdmi_fixed_voltage_config = {
+ .supply_name = "HDMI_EN1",
+ .microvolts = 5000000,
+ .gpio = EXYNOS4_GPE0(1),
+ .enable_high = true,
+ .init_data = &hdmi_fixed_voltage_init_data,
+};
+
+static struct platform_device hdmi_fixed_voltage = {
+ .name = "reg-fixed-voltage",
+ .id = FIXED_REG_ID_HDMI_5V,
+ .dev = {
+ .platform_data = &hdmi_fixed_voltage_config,
+ },
+};
+
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
{
@@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
gpio_direction_output(gpio, 1);
}
+static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
+ .frequency = 300 * 1000,
+ .sda_delay = 200,
+};
+
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
@@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
static struct platform_device mmc0_fixed_voltage = {
.name = "reg-fixed-voltage",
- .id = 0,
+ .id = FIXED_REG_ID_MMC0,
.dev = {
.platform_data = &mmc0_fixed_voltage_config,
},
@@ -692,18 +797,165 @@ static void __init universal_sdhci_init(void)
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
}
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
- /* Camera, To be updated */
-};
-
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
+/* Frame Buffer */
+static struct s3c_fb_pd_win universal_fb_win0 = {
+ .win_mode = {
+ .left_margin = 16,
+ .right_margin = 16,
+ .upper_margin = 2,
+ .lower_margin = 28,
+ .hsync_len = 2,
+ .vsync_len = 1,
+ .xres = 480,
+ .yres = 800,
+ .refresh = 55,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+};
+
+static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
+ .win[0] = &universal_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+ VIDCON0_CLKSEL_LCD,
+ .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+ | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct regulator_consumer_supply cam_i_core_supply =
+ REGULATOR_SUPPLY("core", "0-001f");
+
+static struct regulator_init_data cam_i_core_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cam_i_core_supply,
+};
+
+static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
+ .supply_name = "CAM_I_CORE_1.2V",
+ .microvolts = 1200000,
+ .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
+ .enable_high = 1,
+ .init_data = &cam_i_core_reg_init_data,
+};
+
+static struct platform_device cam_i_core_fixed_reg_dev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
+ .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply cam_s_if_supply =
+ REGULATOR_SUPPLY("d_sensor", "0-001f");
+
+static struct regulator_init_data cam_s_if_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cam_s_if_supply,
+};
+
+static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
+ .supply_name = "CAM_S_IF_1.8V",
+ .microvolts = 1800000,
+ .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
+ .enable_high = 1,
+ .init_data = &cam_s_if_reg_init_data,
+};
+
+static struct platform_device cam_s_if_fixed_reg_dev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
+ .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+ .clk_rate = 166000000UL,
+ .lanes = 2,
+ .alignment = 32,
+ .hs_settle = 12,
+ .phy_enable = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
+#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
+
+static int m5mols_set_power(struct device *dev, int on)
+{
+ gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
+ gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+ return 0;
+}
+
+static struct m5mols_platform_data m5mols_platdata = {
+ .gpio_reset = GPIO_CAM_MEGA_nRST,
+ .reset_polarity = 0,
+ .set_power = m5mols_set_power,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+ I2C_BOARD_INFO("M5MOLS", 0x1F),
+ .platform_data = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info universal_camera_sensors[] = {
+ {
+ .mux_id = 0,
+ .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+ V4L2_MBUS_VSYNC_ACTIVE_LOW,
+ .bus_type = FIMC_MIPI_CSI2,
+ .board_info = &m5mols_board_info,
+ .i2c_bus_num = 0,
+ .clk_frequency = 21600000UL,
+ .csi_data_align = 32,
+ },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+ .isp_info = universal_camera_sensors,
+ .num_clients = ARRAY_SIZE(universal_camera_sensors),
+};
+
+static struct gpio universal_camera_gpios[] = {
+ { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
+ { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
+ { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
+ { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+};
+
+static void universal_camera_init(void)
+{
+ s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+ &s5p_device_mipi_csis0);
+ s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
+ &s5p_device_fimc_md);
+
+ if (gpio_request_array(universal_camera_gpios,
+ ARRAY_SIZE(universal_camera_gpios))) {
+ pr_err("%s: GPIO request failed\n", __func__);
+ return;
+ }
+
+ if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
+ m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
+ else
+ pr_err("Failed to configure 8M_ISP_INT GPIO\n");
+
+ /* Free GPIOs controlled directly by the sensor drivers. */
+ gpio_free(GPIO_CAM_MEGA_nRST);
+ gpio_free(GPIO_CAM_8M_ISP_INT);
+
+ if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
+ pr_err("Camera port A setup failed\n");
+}
+
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
+ &s5p_device_mipi_csis0,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
@@ -712,17 +964,30 @@ static struct platform_device *universal_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
+ &s3c_device_i2c0,
&s3c_device_i2c3,
&s3c_device_i2c5,
+ &s5p_device_i2c_hdmiphy,
+ &hdmi_fixed_voltage,
+ &exynos4_device_pd[PD_TV],
+ &s5p_device_hdmi,
+ &s5p_device_sdo,
+ &s5p_device_mixer,
/* Universal Devices */
&i2c_gpio12,
&universal_gpio_keys,
&s5p_device_onenand,
+ &s5p_device_fimd0,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
+ &exynos4_device_pd[PD_LCD0],
+ &exynos4_device_pd[PD_CAM],
+ &cam_i_core_fixed_reg_dev,
+ &cam_s_if_fixed_reg_dev,
+ &s5p_device_fimc_md,
};
static void __init universal_map_io(void)
@@ -732,6 +997,20 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
+void s5p_tv_setup(void)
+{
+ /* direct HPD to HDMI chip */
+ gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
+
+ gpio_direction_input(EXYNOS4_GPX3(7));
+ s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+ s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+ /* setup dependencies between TV devices */
+ s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+ s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
static void __init universal_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
@@ -740,8 +1019,9 @@ static void __init universal_reserve(void)
static void __init universal_machine_init(void)
{
universal_sdhci_init();
+ s5p_tv_setup();
- i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+ s3c_i2c0_set_platdata(&universal_i2c0_platdata);
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
universal_tsp_init();
@@ -749,15 +1029,28 @@ static void __init universal_machine_init(void)
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL);
+ s5p_i2c_hdmiphy_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+ s5p_fimd0_set_platdata(&universal_lcd_pdata);
+
universal_touchkey_init();
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
ARRAY_SIZE(i2c_gpio12_devs));
+ universal_camera_init();
+
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+ s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+ s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 62e4f4363006..509a435afd4b 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void)
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (soc_is_exynos4212()) {
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+ tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
+ S5P_USE_STANDBYWFE_ISP_ARM);
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ }
+
/* Save Power control register */
asm ("mrc p15, 0, %0, c15, c0, 0"
: "=r" (tmp) : : "cc");
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
index 7ea9eb2a20d2..bba48f5c3e8f 100644
--- a/arch/arm/mach-exynos4/pmu.c
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -16,160 +16,215 @@
#include <mach/regs-clock.h>
#include <mach/pmu.h>
-static void __iomem *sys_powerdown_reg[] = {
- S5P_ARM_CORE0_LOWPWR,
- S5P_DIS_IRQ_CORE0,
- S5P_DIS_IRQ_CENTRAL0,
- S5P_ARM_CORE1_LOWPWR,
- S5P_DIS_IRQ_CORE1,
- S5P_DIS_IRQ_CENTRAL1,
- S5P_ARM_COMMON_LOWPWR,
- S5P_L2_0_LOWPWR,
- S5P_L2_1_LOWPWR,
- S5P_CMU_ACLKSTOP_LOWPWR,
- S5P_CMU_SCLKSTOP_LOWPWR,
- S5P_CMU_RESET_LOWPWR,
- S5P_APLL_SYSCLK_LOWPWR,
- S5P_MPLL_SYSCLK_LOWPWR,
- S5P_VPLL_SYSCLK_LOWPWR,
- S5P_EPLL_SYSCLK_LOWPWR,
- S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
- S5P_CMU_RESET_GPSALIVE_LOWPWR,
- S5P_CMU_CLKSTOP_CAM_LOWPWR,
- S5P_CMU_CLKSTOP_TV_LOWPWR,
- S5P_CMU_CLKSTOP_MFC_LOWPWR,
- S5P_CMU_CLKSTOP_G3D_LOWPWR,
- S5P_CMU_CLKSTOP_LCD0_LOWPWR,
- S5P_CMU_CLKSTOP_LCD1_LOWPWR,
- S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
- S5P_CMU_CLKSTOP_GPS_LOWPWR,
- S5P_CMU_RESET_CAM_LOWPWR,
- S5P_CMU_RESET_TV_LOWPWR,
- S5P_CMU_RESET_MFC_LOWPWR,
- S5P_CMU_RESET_G3D_LOWPWR,
- S5P_CMU_RESET_LCD0_LOWPWR,
- S5P_CMU_RESET_LCD1_LOWPWR,
- S5P_CMU_RESET_MAUDIO_LOWPWR,
- S5P_CMU_RESET_GPS_LOWPWR,
- S5P_TOP_BUS_LOWPWR,
- S5P_TOP_RETENTION_LOWPWR,
- S5P_TOP_PWR_LOWPWR,
- S5P_LOGIC_RESET_LOWPWR,
- S5P_ONENAND_MEM_LOWPWR,
- S5P_MODIMIF_MEM_LOWPWR,
- S5P_G2D_ACP_MEM_LOWPWR,
- S5P_USBOTG_MEM_LOWPWR,
- S5P_HSMMC_MEM_LOWPWR,
- S5P_CSSYS_MEM_LOWPWR,
- S5P_SECSS_MEM_LOWPWR,
- S5P_PCIE_MEM_LOWPWR,
- S5P_SATA_MEM_LOWPWR,
- S5P_PAD_RETENTION_DRAM_LOWPWR,
- S5P_PAD_RETENTION_MAUDIO_LOWPWR,
- S5P_PAD_RETENTION_GPIO_LOWPWR,
- S5P_PAD_RETENTION_UART_LOWPWR,
- S5P_PAD_RETENTION_MMCA_LOWPWR,
- S5P_PAD_RETENTION_MMCB_LOWPWR,
- S5P_PAD_RETENTION_EBIA_LOWPWR,
- S5P_PAD_RETENTION_EBIB_LOWPWR,
- S5P_PAD_RETENTION_ISOLATION_LOWPWR,
- S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
- S5P_XUSBXTI_LOWPWR,
- S5P_XXTI_LOWPWR,
- S5P_EXT_REGULATOR_LOWPWR,
- S5P_GPIO_MODE_LOWPWR,
- S5P_GPIO_MODE_MAUDIO_LOWPWR,
- S5P_CAM_LOWPWR,
- S5P_TV_LOWPWR,
- S5P_MFC_LOWPWR,
- S5P_G3D_LOWPWR,
- S5P_LCD0_LOWPWR,
- S5P_LCD1_LOWPWR,
- S5P_MAUDIO_LOWPWR,
- S5P_GPS_LOWPWR,
- S5P_GPS_ALIVE_LOWPWR,
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+ /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
+ { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
+ { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
+ { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
+ { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
+ { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
+ { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { PMU_TABLE_END,},
};
-static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
- /* { AFTR, LPA, SLEEP }*/
- { 0, 0, 2 }, /* ARM_CORE0 */
- { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
- { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
- { 0, 0, 2 }, /* ARM_CORE1 */
- { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
- { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
- { 0, 0, 2 }, /* ARM_COMMON */
- { 2, 2, 3 }, /* ARM_CPU_L2_0 */
- { 2, 2, 3 }, /* ARM_CPU_L2_1 */
- { 1, 0, 0 }, /* CMU_ACLKSTOP */
- { 1, 0, 0 }, /* CMU_SCLKSTOP */
- { 1, 1, 0 }, /* CMU_RESET */
- { 1, 0, 0 }, /* APLL_SYSCLK */
- { 1, 0, 0 }, /* MPLL_SYSCLK */
- { 1, 0, 0 }, /* VPLL_SYSCLK */
- { 1, 1, 0 }, /* EPLL_SYSCLK */
- { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
- { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
- { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
- { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
- { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
- { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
- { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
- { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
- { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
- { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
- { 1, 1, 0 }, /* CMU_RESET_CAM */
- { 1, 1, 0 }, /* CMU_RESET_TV */
- { 1, 1, 0 }, /* CMU_RESET_MFC */
- { 1, 1, 0 }, /* CMU_RESET_G3D */
- { 1, 1, 0 }, /* CMU_RESET_LCD0 */
- { 1, 1, 0 }, /* CMU_RESET_LCD1 */
- { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
- { 1, 1, 0 }, /* CMU_RESET_GPS */
- { 3, 0, 0 }, /* TOP_BUS */
- { 1, 0, 1 }, /* TOP_RETENTION */
- { 3, 0, 3 }, /* TOP_PWR */
- { 1, 1, 0 }, /* LOGIC_RESET */
- { 3, 0, 0 }, /* ONENAND_MEM */
- { 3, 0, 0 }, /* MODIMIF_MEM */
- { 3, 0, 0 }, /* G2D_ACP_MEM */
- { 3, 0, 0 }, /* USBOTG_MEM */
- { 3, 0, 0 }, /* HSMMC_MEM */
- { 3, 0, 0 }, /* CSSYS_MEM */
- { 3, 0, 0 }, /* SECSS_MEM */
- { 3, 0, 0 }, /* PCIE_MEM */
- { 3, 0, 0 }, /* SATA_MEM */
- { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
- { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
- { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
- { 1, 0, 0 }, /* PAD_RETENTION_UART */
- { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
- { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
- { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
- { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
- { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
- { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
- { 1, 1, 0 }, /* XUSBXTI */
- { 1, 1, 0 }, /* XXTI */
- { 1, 1, 0 }, /* EXT_REGULATOR */
- { 1, 0, 0 }, /* GPIO_MODE */
- { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
- { 7, 0, 0 }, /* CAM */
- { 7, 0, 0 }, /* TV */
- { 7, 0, 0 }, /* MFC */
- { 7, 0, 0 }, /* G3D */
- { 7, 0, 0 }, /* LCD0 */
- { 7, 0, 0 }, /* LCD1 */
- { 7, 7, 0 }, /* MAUDIO */
- { 7, 0, 0 }, /* GPS */
- { 7, 0, 0 }, /* GPS_ALIVE */
+static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+ { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
+ { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
+ { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
+ { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
+ { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
+ { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
+ /* XXX_OPTION register should be set other field */
+ { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
+ { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
+ { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
+ { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
+ { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
+ { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
+ { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
+ { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
+ { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
+ { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
+ { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
+ { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
+ { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
+ { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
+ { PMU_TABLE_END,},
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
- unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+ unsigned int i;
+
+ for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
+ __raw_writel(exynos4_pmu_config[i].val[mode],
+ exynos4_pmu_config[i].reg);
+}
+
+static int __init exynos4_pmu_init(void)
+{
+ exynos4_pmu_config = exynos4210_pmu_config;
+
+ if (soc_is_exynos4210()) {
+ exynos4_pmu_config = exynos4210_pmu_config;
+ pr_info("EXYNOS4210 PMU Initialize\n");
+ } else if (soc_is_exynos4212()) {
+ exynos4_pmu_config = exynos4212_pmu_config;
+ pr_info("EXYNOS4212 PMU Initialize\n");
+ } else {
+ pr_info("EXYNOS4: PMU not supported\n");
+ }
- for (; count > 0; count--)
- __raw_writel(sys_powerdown_val[count - 1][mode],
- sys_powerdown_reg[count - 1]);
+ return 0;
}
+arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index 1e83f8cf236d..92937b410906 100644
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -10,16 +10,7 @@
* published by the Free Software Foundation.
*/
-#include <linux/kernel.h>
#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = {
[2] = "sclk_mmc", /* mmc_bus */
[3] = NULL,
};
-
-void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
- struct mmc_ios *ios, struct mmc_card *card)
-{
- u32 ctrl2, ctrl3;
-
- /* don't need to alter anything according to card-type */
-
- ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-
- /* select base clock source to HCLK */
-
- ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-
- /*
- * clear async mode, enable conflict mask, rx feedback ctrl, SD
- * clk hold and no use debounce count
- */
-
- ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
- S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
- S3C_SDHCI_CTRL2_ENFBCLKRX |
- S3C_SDHCI_CTRL2_DFCNT_NONE |
- S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
- /* Tx and Rx feedback clock delay control */
-
- if (ios->clock < 25 * 1000000)
- ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
- S3C_SDHCI_CTRL3_FCSEL2 |
- S3C_SDHCI_CTRL3_FCSEL1 |
- S3C_SDHCI_CTRL3_FCSEL0);
- else
- ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
- writel(ctrl2, r + S3C_SDHCI_CONTROL2);
- writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
deleted file mode 100644
index 0984078f1eba..000000000000
--- a/arch/arm/mach-exynos4/sleep.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-exynos4/sleep.S
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- * Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
- .text
-
- /*
- * sleep magic, to allow the bootloader to check for an valid
- * image to resume to. Must be the first word before the
- * s3c_cpu_resume entry.
- */
-
- .word 0x2bedf00d
-
- /*
- * s3c_cpu_resume
- *
- * resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
- */
-
-ENTRY(s3c_cpu_resume)
- b cpu_resume
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-24 15:34:30 +0000