diff options
author | Alex Shi <alex.shi@linaro.org> | 2016-09-20 10:17:00 +0800 |
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committer | Alex Shi <alex.shi@linaro.org> | 2016-09-20 10:17:00 +0800 |
commit | d2d693d1ba7d93ec7c5db8aca2da29a4c91f6782 (patch) | |
tree | 41920dcc166c491e7192eb1e3ba3861dff479abf /tools/perf/arch/x86/util/intel-pt.c | |
parent | 573787341e57a73bf027c2ea3bdf18dc298ae0a0 (diff) | |
parent | 1d074db69c46d62ce82b331c2080e2fcb710bf4a (diff) |
Merge remote-tracking branch 'lts/linux-4.4.y' into linux-linaro-lsk-v4.4
Conflicts:
set ARM64_WORKAROUND_CAVIUM_27456 to 12 in
arch/arm64/include/asm/cpufeature.h
and add asm/memory.h in arch/arm64/kernel/entry.S
Diffstat (limited to 'tools/perf/arch/x86/util/intel-pt.c')
-rw-r--r-- | tools/perf/arch/x86/util/intel-pt.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index e5c1f2e21f87..de3965c4e4aa 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -501,7 +501,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, struct intel_pt_recording *ptr = container_of(itr, struct intel_pt_recording, itr); struct perf_pmu *intel_pt_pmu = ptr->intel_pt_pmu; - bool have_timing_info; + bool have_timing_info, need_immediate = false; struct perf_evsel *evsel, *intel_pt_evsel = NULL; const struct cpu_map *cpus = evlist->cpus; bool privileged = geteuid() == 0 || perf_event_paranoid() < 0; @@ -655,6 +655,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, ptr->have_sched_switch = 3; } else { opts->record_switch_events = true; + need_immediate = true; if (cpu_wide) ptr->have_sched_switch = 3; else @@ -700,6 +701,9 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, tracking_evsel->attr.freq = 0; tracking_evsel->attr.sample_period = 1; + if (need_immediate) + tracking_evsel->immediate = true; + /* In per-cpu case, always need the time of mmap events etc */ if (!cpu_map__empty(cpus)) { perf_evsel__set_sample_bit(tracking_evsel, TIME); |