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authorAlex Shi <alex.shi@linaro.org>2017-03-20 12:03:13 +0800
committerAlex Shi <alex.shi@linaro.org>2017-03-20 12:03:13 +0800
commit89e7fad96be88f30f491bf227d864bf5e8e701b2 (patch)
tree6316161ebd26b780991ff8632471fbbfa3af7ea8 /include/soc/at91/at91sam9_ddrsdr.h
parent5b0250d2571ee75ca3c0b34579c3e90bc2bd9c6a (diff)
parent1c563c0006661025d7a6c9bc85fc889a4e8a1c06 (diff)
Diffstat (limited to 'include/soc/at91/at91sam9_ddrsdr.h')
-rw-r--r--include/soc/at91/at91sam9_ddrsdr.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
index dc10c52e0e91..393362bdb860 100644
--- a/include/soc/at91/at91sam9_ddrsdr.h
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -81,6 +81,7 @@
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
+#define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
@@ -96,7 +97,9 @@
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
+#define AT91_DDRSDRC_MD_LPDDR3 5
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
+#define AT91_DDRSDRC_MD_LPDDR2 7
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)