diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-06 14:43:13 -0700 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-07 11:37:18 -0700 |
| commit | d3572532993c7e8635ad8e5b50f8f613bf855ee2 (patch) | |
| tree | 4e6b9b4650bbc60add44d824469b357b831b2264 /drivers | |
| parent | b5e350f919acb8ef6961bc1b62e395f53cea123a (diff) | |
agp/intel: Use CPU physical address, not bus address, for ioremap()
In i810_setup(), i830_setup(), and i9xx_setup(), we use the result of
pci_bus_address() as an argument to ioremap() and to compute gtt_phys_addr.
These should use pci_resource_start() instead because we want the CPU
physical address, not the bus address.
If there were an AGP device behind a host bridge that translated addresses,
e.g., a PNP0A08 device with _TRA != 0, this would fix a bug. I'm not aware
of any of those, but they are possible.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/char/agp/intel-gtt.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index dd8b66a617dc..ad5da1ffcbe9 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -172,7 +172,7 @@ static void i8xx_destroy_pages(struct page *page) #define I810_GTT_ORDER 4 static int i810_setup(void) { - u32 reg_addr; + phys_addr_t reg_addr; char *gtt_table; /* i81x does not preallocate the gtt. It's always 64kb in size. */ @@ -181,7 +181,7 @@ static int i810_setup(void) return -ENOMEM; intel_private.i81x_gtt_table = gtt_table; - reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR); + reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); intel_private.registers = ioremap(reg_addr, KB(64)); if (!intel_private.registers) @@ -782,9 +782,9 @@ EXPORT_SYMBOL(intel_enable_gtt); static int i830_setup(void) { - u32 reg_addr; + phys_addr_t reg_addr; - reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR); + reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); intel_private.registers = ioremap(reg_addr, KB(64)); if (!intel_private.registers) @@ -1102,10 +1102,10 @@ static void i965_write_entry(dma_addr_t addr, static int i9xx_setup(void) { - u32 reg_addr; + phys_addr_t reg_addr; int size = KB(512); - reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR); + reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); intel_private.registers = ioremap(reg_addr, size); if (!intel_private.registers) @@ -1114,7 +1114,7 @@ static int i9xx_setup(void) switch (INTEL_GTT_GEN) { case 3: intel_private.gtt_phys_addr = - pci_bus_address(intel_private.pcidev, I915_PTE_BAR); + pci_resource_start(intel_private.pcidev, I915_PTE_BAR); break; case 5: intel_private.gtt_phys_addr = reg_addr + MB(2); |