diff options
| author | Pratyush Anand <pratyush.anand@st.com> | 2012-06-21 17:44:28 +0530 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2012-06-22 13:21:54 +0300 |
| commit | 45627ac6a4f063d19b0bd9863d20ac1dabda99a7 (patch) | |
| tree | 471d88cdf2a733a0531e2c755adb5cc8fb389e12 /drivers/usb/dwc3/core.c | |
| parent | 45c396ce6bdad60ee94e6eed8cc7f09678651102 (diff) | |
USB: DWC3: Put 100 ms delay for phy to be stable
Before taking core out of reset phy must be stable. So wait for 100ms
after clear phy reset.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc3/core.c')
| -rw-r--r-- | drivers/usb/dwc3/core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 49c060205c9a..ac151e9acf20 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -148,6 +148,8 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc) reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + mdelay(100); + /* After PHYs are stable we can take Core out of reset state */ reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_CORESOFTRESET; |