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authorMika Westerberg <mika.westerberg@linux.intel.com>2013-03-05 12:05:17 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-03-12 18:30:56 +0000
commit0054e28dc9d2d7c43b569ed5d491bc8bc2f903a9 (patch)
tree90e0c1c28f991899c9a3adbebacb6da3c36165fc /drivers/spi/spi-pxa2xx.c
parentc134634077942404a285f6b64bc1ce5932ac22fe (diff)
downloadlinux-linaro-stable-0054e28dc9d2d7c43b569ed5d491bc8bc2f903a9.tar.gz
spi/pxa2xx: enable multiblock DMA transfers for LPSS devices
Intel LPSS SPI controllers need to have bit 0 (disable_ssp_dma_finish) set in SSP_REG in order to properly perform DMA transfers spanning over multiple blocks. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
-rw-r--r--drivers/spi/spi-pxa2xx.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 90b27a3508a6..c6d5b97c7240 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -68,6 +68,7 @@ MODULE_ALIAS("platform:pxa2xx-spi");
#define LPSS_TX_HITHRESH_DFLT 224
/* Offset from drv_data->lpss_base */
+#define SSP_REG 0x0c
#define SPI_CS_CONTROL 0x18
#define SPI_CS_CONTROL_SW_MODE BIT(0)
#define SPI_CS_CONTROL_CS_HIGH BIT(1)
@@ -138,6 +139,10 @@ detection_done:
/* Enable software chip select control */
value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
__lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
+
+ /* Enable multiblock DMA transfers */
+ if (drv_data->master_info->enable_dma)
+ __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
}
static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)