path: root/drivers/pci/intel-iommu.c
diff options
authorDavid Woodhouse <David.Woodhouse@intel.com>2010-06-15 10:57:57 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-06-15 10:57:57 +0100
commit2d9e667efdfb4e986074d98e7d9a424003c7c43b (patch)
treea3436795620225e16c676882caf6822e219b98b6 /drivers/pci/intel-iommu.c
parent00dfff77e7184140dc45724c7232e99302f6bf97 (diff)
intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.
Certain revisions of this chipset appear to be broken. There is a shadow GTT which mirrors the real GTT but contains pre-translated physical addresses, for performance reasons. When a GTT update happens, the translations are done once and the resulting physical addresses written back to the shadow GTT. Except sometimes, the physical address is actually written back to the _real_ GTT, not the shadow GTT. Thus we start to see faults when that physical address is fed through translation again. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/pci/intel-iommu.c')
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index bf8fd913d064..c9171be74564 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -340,7 +340,7 @@ int dmar_disabled = 0;
int dmar_disabled = 1;
-static int __initdata dmar_map_gfx = 1;
+static int dmar_map_gfx = 1;
static int dmar_forcedac;
static int intel_iommu_strict;
@@ -3721,6 +3721,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
rwbf_quirk = 1;
+ /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
+ if (dev->revision == 0x07) {
+ printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
+ dmar_map_gfx = 0;
+ }