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authorTodd Fujinaka <todd.fujinaka@intel.com>2014-05-08 23:20:24 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2014-05-27 02:10:44 -0700
commit18cae6f7bb65bdb272f844525f7acd6d464a8541 (patch)
tree1d67f8e748a8da0c2788a1f24f02d4a7c632b974 /drivers/net/ethernet/intel/igb/e1000_phy.h
parentc6f3148c5bcad2eb9ff1c700d6c79815173aed35 (diff)
downloadlinux-linaro-stable-18cae6f7bb65bdb272f844525f7acd6d464a8541.tar.gz
igb: remove redundant PHY power down register write
One of the registers used to power down the PHY was found to be wrong (should be bit 2 not bit 1) on further inspection it was also found to be redundant. Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_phy.h')
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_phy.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h
index fe921e29dda8..7af4ffab0285 100644
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
@@ -151,7 +151,6 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw);
#define GS40G_MAC_LB 0x4140
#define GS40G_MAC_SPEED_1G 0X0006
#define GS40G_COPPER_SPEC 0x0010
-#define GS40G_CS_POWER_DOWN 0x0002
#define GS40G_LINE_LB 0x4000
/* SFP modules ID memory locations */