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authorBen Skeggs <bskeggs@redhat.com>2012-02-07 09:59:54 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:14:58 +1000
commit1ae73f2f16f1a905ada71e2a190d5760b4f17ed8 (patch)
tree10ee30114c0333feed5b80bffb571d9b935c70d0 /drivers/gpu/drm/nouveau/nvc0_pm.c
parent44ab8cc56c45ca781371a4a77f35da19cf5db028 (diff)
downloadlinux-linaro-stable-1ae73f2f16f1a905ada71e2a190d5760b4f17ed8.tar.gz
drm/nvc0/pm: restrict pll mode to clocks that can actually use it
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvc0_pm.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index e9992f62c1c0..ce65f81bb871 100644
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
- if (clk0 != freq) {
+ if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else