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| author | Alex Shi <alex.shi@linaro.org> | 2016-05-20 12:16:43 +0800 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2016-05-20 12:16:43 +0800 |
| commit | 1d53a9c6e6c7bc32ecfbbb024ab7a1955122c526 (patch) | |
| tree | 977cfcbda4ef5173a9455e66350b610e96f1eeef /drivers/gpu/drm/i915/intel_pm.c | |
| parent | a8a1fcae2dcc97748b7cafa7cb2745de1f35a8a6 (diff) | |
| parent | 510d0a3f869611dcd001a2b7627fa5dded4579af (diff) | |
Merge branch 'linux-linaro-lsk-v4.4' into linux-linaro-lsk-v4.4-rtlsk-v4.4-16.05-rt
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f091ad12d694..0a68d2ec89dc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6620,6 +6620,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + /* + * Wait at least 100 clocks before re-enabling clock gating. See + * the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); I915_WRITE(GEN7_MISCCPCTL, misccpctl); /* |