diff options
author | Alex Shi <alex.shi@linaro.org> | 2016-07-01 14:33:41 +0800 |
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committer | Alex Shi <alex.shi@linaro.org> | 2016-07-01 14:34:26 +0800 |
commit | 439863d92fda525a8f3b326a24490e91c70f0496 (patch) | |
tree | ec25b3ae200d75f2be939a7da5305537dd9172f9 /drivers/edac/sb_edac.c | |
parent | 43c981bd2d8af8d91726be1fac389cdce47dce1e (diff) | |
parent | 95123c0b81d9478b8155fe15093b88f57ef7d0bd (diff) |
Merge remote-tracking branch 'lts/linux-4.1.y' into linux-linaro-lsk-v4.1lsk-v4.1-16.06
Conflicts:
adopt s/cpufreq_val/cpufreq_freqs in drivers/thermal/cpu_cooling.c
Diffstat (limited to 'drivers/edac/sb_edac.c')
-rw-r--r-- | drivers/edac/sb_edac.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index a7e7be0a8ae8..cb46c468b01e 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -218,8 +218,11 @@ static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, }; -#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) -#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) +#define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ + GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) + +#define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ + GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) /* Device 16, functions 2-7 */ @@ -1101,14 +1104,14 @@ static void get_memory_layout(const struct mem_ctl_info *mci) pci_read_config_dword(pvt->pci_tad[i], rir_offset[j][k], ®); - tmp_mb = RIR_OFFSET(reg) << 6; + tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; gb = div_u64_rem(tmp_mb, 1024, &mb); edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", i, j, k, gb, (mb*1000)/1024, ((u64)tmp_mb) << 20L, - (u32)RIR_RNK_TGT(reg), + (u32)RIR_RNK_TGT(pvt->info.type, reg), reg); } } @@ -1432,7 +1435,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci, pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); - *rank = RIR_RNK_TGT(reg); + *rank = RIR_RNK_TGT(pvt->info.type, reg); edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", n_rir, |