diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2015-09-28 18:57:03 +0300 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2015-10-27 22:13:05 -0400 |
| commit | 5a1c58d34f326eb02c67235876b5851bc202d242 (patch) | |
| tree | 155b93ca607714926c6ce1840d88620e78542f1d /drivers/dma | |
| parent | 3f052171735fc50371f5bd8beacbb5e44b9cb9da (diff) | |
dmaengine: dw: properly read DWC_PARAMS register
[ Upstream commit 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf ]
In case we have less than maximum allowed channels (8) and autoconfiguration is
enabled the DWC_PARAMS read is wrong because it uses different arithmetic to
what is needed for channel priority setup.
Re-do the caclulations properly. This now works on AVR32 board well.
Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers)
Cc: yitian.bu@tangramtek.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/dw/core.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 244722170410..9da24a5e1561 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1579,7 +1579,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) INIT_LIST_HEAD(&dw->dma.channels); for (i = 0; i < nr_channels; i++) { struct dw_dma_chan *dwc = &dw->chan[i]; - int r = nr_channels - i - 1; dwc->chan.device = &dw->dma; dma_cookie_init(&dwc->chan); @@ -1591,7 +1590,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* 7 is highest priority & 0 is lowest. */ if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) - dwc->priority = r; + dwc->priority = nr_channels - i - 1; else dwc->priority = i; @@ -1610,6 +1609,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* Hardware configuration */ if (autocfg) { unsigned int dwc_params; + unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; void __iomem *addr = chip->regs + r * sizeof(u32); dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |