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authorTim Chen <tim.c.chen@linux.intel.com>2012-09-27 15:44:22 -0700
committerHerbert Xu <herbert@gondor.apana.org.au>2012-10-15 22:18:24 +0800
commit6a8ce1ef3940e0cab5ff5f11e1cff5301f83fef6 (patch)
tree3c407b6f40b1dfdf01310348996dc9b939f4e600 /crypto
parent35b80920d4f0253fed03a1c3a345df8578dbd057 (diff)
downloadlinux-linaro-stable-6a8ce1ef3940e0cab5ff5f11e1cff5301f83fef6.tar.gz
crypto: crc32c - Optimize CRC32C calculation with PCLMULQDQ instruction
This patch adds the crc_pcl function that calculates CRC32C checksum using the PCLMULQDQ instruction on processors that support this feature. This will provide speedup over using CRC32 instruction only. The usage of PCLMULQDQ necessitate the invocation of kernel_fpu_begin and kernel_fpu_end and incur some overhead. So the new crc_pcl function is only invoked for buffer size of 512 bytes or more. Larger sized buffers will expect to see greater speedup. This feature is best used coupled with eager_fpu which reduces the kernel_fpu_begin/end overhead. For buffer size of 1K the speedup is around 1.6x and for buffer size greater than 4K, the speedup is around 3x compared to original implementation in crc32c-intel module. Test was performed on Sandy Bridge based platform with constant frequency set for cpu. A white paper detailing the algorithm can be found here: http://download.intel.com/design/intarch/papers/323405.pdf Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'crypto')
-rw-r--r--crypto/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 6563366bae80..b901b590635f 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -324,9 +324,19 @@ config CRYPTO_CRC32C
by iSCSI for header and data digests and by others.
See Castagnoli93. Module will be crc32c.
+config CRYPTO_CRC32C_X86_64
+ bool
+ depends on X86 && 64BIT
+ select CRYPTO_HASH
+ help
+ In Intel processor with SSE4.2 supported, the processor will
+ support CRC32C calculation using hardware accelerated CRC32
+ instruction optimized with PCLMULQDQ instruction when available.
+
config CRYPTO_CRC32C_INTEL
tristate "CRC32c INTEL hardware acceleration"
depends on X86
+ select CRYPTO_CRC32C_X86_64 if 64BIT
select CRYPTO_HASH
help
In Intel processor with SSE4.2 supported, the processor will