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authorWill Deacon <will.deacon@arm.com>2012-01-20 11:55:54 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-23 10:20:04 +0000
commitf0d5375e3c7b5d7f128af03c5271c328faeb3ae7 (patch)
tree6d1a621761d37727a7c88415824fb9736d3f19d5 /arch
parent06e9905152cd124c53f571296e9904ea89c1a39a (diff)
downloadlinux-linaro-stable-f0d5375e3c7b5d7f128af03c5271c328faeb3ae7.tar.gz
ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
The linker script assumes a cacheline size of 32 bytes when aligning the .data..cacheline_aligned and .data..percpu sections. This patch updates the script to use L1_CACHE_BYTES, which should be set to 64 on platforms that require it. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/vmlinux.lds.S7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index f76e75548670..1077e4ff6f3c 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -4,6 +4,7 @@
*/
#include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/page.h>
@@ -181,7 +182,7 @@ SECTIONS
}
#endif
- PERCPU_SECTION(32)
+ PERCPU_SECTION(L1_CACHE_BYTES)
#ifdef CONFIG_XIP_KERNEL
__data_loc = ALIGN(4); /* location in binary */
@@ -212,8 +213,8 @@ SECTIONS
#endif
NOSAVE_DATA
- CACHELINE_ALIGNED_DATA(32)
- READ_MOSTLY_DATA(32)
+ CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
+ READ_MOSTLY_DATA(L1_CACHE_BYTES)
/*
* The exception fixup table (might need resorting at runtime)