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authorWill Deacon <will.deacon@arm.com>2012-01-20 12:10:18 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-23 10:20:06 +0000
commit612539e81f655f6ac73c7af1da8701c1ee618aee (patch)
treea442b17625ad28e282c4ddb0f786ccdfbe4f8bf4 /arch
parent868dbf905245a524496a0535982ed21ad3be5585 (diff)
downloadlinux-linaro-stable-612539e81f655f6ac73c7af1da8701c1ee618aee.tar.gz
ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
On v7, we use the same cache maintenance instructions for data lines as for unified lines. This was not the case for v6, where HARVARD_CACHE was defined to indicate the L1 cache topology. This patch removes the erroneous compile-time check for HARVARD_CACHE in proc-v7.S, ensuring that we perform I-side invalidation at boot. Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: stable <stable@vger.kernel.org> Acked-by: Catalin Marinas <Catalin.Marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mm/proc-v7.S6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b15597400105..0404ccbb8aa3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
* Initialise TLB, Caches, and MMU state ready to switch the MMU
* on. Return in r0 the new CP15 C1 control register setting.
*
- * We automatically detect if we have a Harvard cache, and use the
- * Harvard cache control instructions insead of the unified cache
- * control instructions.
- *
* This should be able to cover all ARMv7 cores.
*
* It is assumed that:
@@ -251,9 +247,7 @@ __v7_setup:
#endif
3: mov r10, #0
-#ifdef HARVARD_CACHE
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
-#endif
dsb
#ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs