|author||Keshavamurthy, Anil S <email@example.com>||2007-10-21 16:41:41 -0700|
|committer||Linus Torvalds <firstname.lastname@example.org>||2007-10-22 08:13:18 -0700|
Intel IOMMU: DMAR detection and parsing logic
This patch supports the upcomming Intel IOMMU hardware a.k.a. Intel(R) Virtualization Technology for Directed I/O Architecture and the hardware spec for the same can be found here http://www.intel.com/technology/virtualization/index.htm FAQ! (questions from akpm, answers from ak) > So... what's all this code for? > > I assume that the intent here is to speed things up under Xen, etc? Yes in some cases, but not this code. That would be the Xen version of this code that could potentially assign whole devices to guests. I expect this to be only useful in some special cases though because most hardware is not virtualizable and you typically want an own instance for each guest. Ok at some point KVM might implement this too; i likely would use this code for this. > Do we > have any benchmark results to help us to decide whether a merge would be > justified? The main advantage for doing it in the normal kernel is not performance, but more safety. Broken devices won't be able to corrupt memory by doing random DMA. Unfortunately that doesn't work for graphics yet, for that need user space interfaces for the X server are needed. There are some potential performance benefits too: - When you have a device that cannot address the complete address range an IOMMU can remap its memory instead of bounce buffering. Remapping is likely cheaper than copying. - The IOMMU can merge sg lists into a single virtual block. This could potentially speed up SG IO when the device is slow walking SG lists. [I long ago benchmarked 5% on some block benchmark with an old MPT Fusion; but it probably depends a lot on the HBA] And you get better driver debugging because unexpected memory accesses from the devices will cause a trappable event. > > Does it slow anything down? It adds more overhead to each IO so yes. This patch: Add support for early detection and parsing of DMAR's (DMA Remapping) reported to OS via ACPI tables. DMA remapping(DMAR) devices support enables independent address translations for Direct Memory Access(DMA) from Devices. These DMA remapping devices are reported via ACPI tables and includes pci device scope covered by these DMA remapping device. For detailed info on the specification of "Intel(R) Virtualization Technology for Directed I/O Architecture" please see http://www.intel.com/technology/virtualization/index.htm Signed-off-by: Anil S Keshavamurthy <email@example.com> Cc: Andi Kleen <firstname.lastname@example.org> Cc: Peter Zijlstra <email@example.com> Cc: Muli Ben-Yehuda <firstname.lastname@example.org> Cc: "Siddha, Suresh B" <email@example.com> Cc: Arjan van de Ven <firstname.lastname@example.org> Cc: Ashok Raj <email@example.com> Cc: "David S. Miller" <firstname.lastname@example.org> Cc: Christoph Lameter <email@example.com> Cc: Greg KH <firstname.lastname@example.org> Cc: Len Brown <email@example.com> Signed-off-by: Andrew Morton <firstname.lastname@example.org> Signed-off-by: Linus Torvalds <email@example.com>
Diffstat (limited to 'arch/x86_64')
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig
index aab25f3ba3ce..5c9aaed589a5 100644
@@ -750,6 +750,17 @@ config PCI_DOMAINS
depends on PCI
+ bool "Support for DMA Remapping Devices (EXPERIMENTAL)"
+ depends on PCI_MSI && ACPI && EXPERIMENTAL
+ default y
+ DMA remapping(DMAR) devices support enables independent address
+ translations for Direct Memory Access(DMA) from Devices.
+ These DMA remapping devices are reported via ACPI tables
+ and includes pci device scope covered by these DMA
+ remapping device.