diff options
| author | John David Anglin <dave.anglin@bell.net> | 2013-06-29 16:42:12 -0400 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2013-07-09 22:09:22 +0200 |
| commit | e8d8fc219f9a0e63e7fb927881e6f4db8e7d34df (patch) | |
| tree | 6c1eedad4943ec3ed06e689c911fa1d66d34ee4c /arch/parisc/kernel | |
| parent | 92b59929825d67db575043a76651865d16873b36 (diff) | |
parisc: Ensure volatile space register %sr1 is not clobbered
I still see the occasional random segv on rp3440. Looking at one of
these (a code 15), it appeared the problem must be with the cache
handling of anonymous pages. Reviewing this, I noticed that the space
register %sr1 might be being clobbered when we flush an anonymous page.
Register %sr1 is used for TLB purges in a couple of places. These
purges are needed on PA8800 and PA8900 processors to ensure cache
consistency of flushed cache lines.
The solution here is simply to move the %sr1 load into the TLB lock
region needed to ensure that one purge executes at a time on SMP
systems. This was already the case for one use. After a few days of
operation, I haven't had a random segv on my rp3440.
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Cc: <stable@vger.kernel.org> # 3.10
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/kernel')
| -rw-r--r-- | arch/parisc/kernel/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index 65fb4cbc3a0f..2e65aa54bd10 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -440,8 +440,8 @@ void __flush_tlb_range(unsigned long sid, unsigned long start, else { unsigned long flags; - mtsp(sid, 1); purge_tlb_start(flags); + mtsp(sid, 1); if (split_tlb) { while (npages--) { pdtlb(start); |