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authorKevin Hilman <khilman@linaro.org>2015-09-14 14:20:38 -0700
committerKevin Hilman <khilman@linaro.org>2015-09-14 14:20:38 -0700
commit705e0fe41b54f2dea954ebd692a870a36b04ce76 (patch)
treedc1c9e774d068ffac89fc9851c921c61cf44677d /arch/mips/mti-malta/malta-time.c
parent373cea9e2c9c6495a80efdae55cf2114f384a75b (diff)
parentc765e5c15e7d23d2b8b37fafdafc63c0ea75fabf (diff)
* linux-linaro-lsk-v3.14: (66 commits) Linux 3.14.52 arm64: KVM: Fix host crash when injecting a fault into a 32bit guest SCSI: Fix NULL pointer dereference in runtime PM arm64/mm: Remove hack in mmap randomize layout crypto: caam - fix memory corruption in ahash_final_ctx regmap: regcache-rbtree: Clean new present bits on present bitmap resize libfc: Fix fc_fcp_cleanup_each_cmd() libfc: Fix fc_exch_recv_req() error path drm/vmwgfx: Fix execbuf locking issues drm/radeon: add new OLAND pci id EDAC, ppc4xx: Access mci->csrows array elements properly localmodconfig: Use Kbuild files too dm thin metadata: delete btrees when releasing metadata snapshot perf: Fix PERF_EVENT_IOC_PERIOD migration race perf: Fix fasync handling on inherited events xen-blkfront: don't add indirect pages to list when !feature_persistent mm/hwpoison: fix page refcount of unknown non LRU page ipc/sem.c: update/correct memory barriers ipc,sem: fix use after free on IPC_RMID after a task using same semaphore set exits arm64: el0_dbg does not set link reg for return to user path, breaks debug ...
Diffstat (limited to 'arch/mips/mti-malta/malta-time.c')
-rw-r--r--arch/mips/mti-malta/malta-time.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 319009912142..d4ab447f7850 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -168,14 +168,17 @@ unsigned int get_c0_compare_int(void)
static void __init init_rtc(void)
{
- /* stop the clock whilst setting it up */
- CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
+ unsigned char freq, ctrl;
- /* 32KHz time base */
- CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
+ /* Set 32KHz time base if not already set */
+ freq = CMOS_READ(RTC_FREQ_SELECT);
+ if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
+ CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
- /* start the clock */
- CMOS_WRITE(RTC_24H, RTC_CONTROL);
+ /* Ensure SET bit is clear so RTC can run */
+ ctrl = CMOS_READ(RTC_CONTROL);
+ if (ctrl & RTC_SET)
+ CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
}
void __init plat_time_init(void)