diff options
| author | Steven J. Hill <Steven.Hill@imgtec.com> | 2014-01-17 15:03:50 -0600 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-06 21:25:21 +0100 |
| commit | 442e14a2c55e55f208bf87e3686396b4ff17ebf6 (patch) | |
| tree | 9370c3907bb6b07027a95181d2e5ee3961641ec3 /arch/mips/mm | |
| parent | 02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e (diff) | |
MIPS: Add 1074K CPU support explicitly.
The 1074K is a multiprocessing coherent processing system (CPS) based
on modified 74K cores. This patch makes the 1074K an actual unique
CPU type, instead of a 74K derivative, which it is not.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6389/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 3 | ||||
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
3 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 8f1d549d5132..ae810320875e 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1113,9 +1113,10 @@ static void probe_pcache(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: - if (current_cpu_type() == CPU_74K) + if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) alias_74k_erratum(c); if (!(read_c0_config7() & MIPS_CONF7_IAR) && (c->icache.waysize > PAGE_SIZE)) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 7a56aee5fce7..7b3977035a46 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -76,6 +76,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_BMIPS5000: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index b234b1b5ccad..151ca264c8a6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -509,6 +509,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, switch (current_cpu_type()) { case CPU_M14KC: case CPU_74K: + case CPU_1074K: case CPU_PROAPTIV: break; |