diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-01-30 17:21:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-06 21:25:21 +0100 |
| commit | 02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e (patch) | |
| tree | 08224e4eb6d1b1471cc3322b626250e2d82bce7e /arch/mips/mm | |
| parent | 0414855fdc4a40da05221fc6062cccbc0c30f169 (diff) | |
MIPS: mm: c-r4k: Detect instruction cache aliases
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c14259edd53f..8f1d549d5132 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1117,9 +1117,14 @@ static void probe_pcache(void) case CPU_PROAPTIV: if (current_cpu_type() == CPU_74K) alias_74k_erratum(c); - if ((read_c0_config7() & (1 << 16))) { - /* effectively physically indexed dcache, - thus no virtual aliases. */ + if (!(read_c0_config7() & MIPS_CONF7_IAR) && + (c->icache.waysize > PAGE_SIZE)) + c->icache.flags |= MIPS_CACHE_ALIASES; + if (read_c0_config7() & MIPS_CONF7_AR) { + /* + * Effectively physically indexed dcache, + * thus no virtual aliases. + */ c->dcache.flags |= MIPS_CACHE_PINDEX; break; } |