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| author | Alex Shi <alex.shi@linaro.org> | 2016-04-11 10:23:11 +0800 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2016-04-11 10:23:11 +0800 |
| commit | bfbd381ea0ca274e4c07ea62acaaeac31829cd5d (patch) | |
| tree | 0531122e023ecbf1ecf9416fc1111955b10ea68b /arch/arm64/mm | |
| parent | 906d9eadd3b6698fa6ceb9bcdf41da6aa56d0a24 (diff) | |
| parent | 115d588693b6f8f9cfad409c091225d4095159e3 (diff) | |
Merge tag 'v4.1.20-rt23' of git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-stable-rt into linux-linaro-lsk-v4.1-rt
Linux 4.1.20-rt23
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/mmu.c | 3 | ||||
| -rw-r--r-- | arch/arm64/mm/pageattr.c | 3 | ||||
| -rw-r--r-- | arch/arm64/mm/proc-macros.S | 12 | ||||
| -rw-r--r-- | arch/arm64/mm/proc.S | 5 |
4 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 5b8b664422d3..cb34eb8bbb9d 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -450,6 +450,9 @@ void __init paging_init(void) empty_zero_page = virt_to_page(zero_page); + /* Ensure the zero page is visible to the page table walker */ + dsb(ishst); + /* * TTBR0 is only used for the identity mapping at this stage. Make it * point to zero page to avoid speculatively fetching new entries. diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index e47ed1c5dce1..545710f854f8 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -57,6 +57,9 @@ static int change_memory_common(unsigned long addr, int numpages, if (end < MODULES_VADDR || end >= MODULES_END) return -EINVAL; + if (!numpages) + return 0; + data.set_mask = set_mask; data.clear_mask = clear_mask; diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S index 4c4d93c4bf65..d69dffffaa89 100644 --- a/arch/arm64/mm/proc-macros.S +++ b/arch/arm64/mm/proc-macros.S @@ -62,3 +62,15 @@ bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH #endif .endm + +/* + * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present + */ + .macro reset_pmuserenr_el0, tmpreg + mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer + sbfx \tmpreg, \tmpreg, #8, #4 + cmp \tmpreg, #1 // Skip if no PMU present + b.lt 9000f + msr pmuserenr_el0, xzr // Disable PMU access from EL0 +9000: + .endm diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index cdd754e19b9b..d253908a988d 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -165,6 +165,7 @@ ENTRY(cpu_do_resume) */ ubfx x11, x11, #1, #1 msr oslar_el1, x11 + reset_pmuserenr_el0 x0 // Disable PMU access from EL0 mov x0, x12 dsb nsh // Make sure local tlb invalidation completed isb @@ -202,7 +203,9 @@ ENTRY(__cpu_setup) mov x0, #3 << 20 msr cpacr_el1, x0 // Enable FP/ASIMD - msr mdscr_el1, xzr // Reset mdscr_el1 + mov x0, #1 << 12 // Reset mdscr_el1 and disable + msr mdscr_el1, x0 // access to the DCC from EL0 + reset_pmuserenr_el0 x0 // Disable PMU access from EL0 /* * Memory region attributes for LPAE: * |