path: root/arch/arm64/kernel/head.S
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authorCatalin Marinas <catalin.marinas@arm.com>2014-07-24 14:14:42 +0100
committerChristoffer Dall <christoffer.dall@linaro.org>2014-10-02 20:50:54 +0200
commit8cbfd57948a16fe813e72e6b0ccb36b6417a78d8 (patch)
tree5dcfcaa0af8f3f517b9a147388f9d22e3fba187a /arch/arm64/kernel/head.S
parenta1e3b5e1f3bb785660db2d1078ba3a7b57ed01bd (diff)
arm64: gicv3: Allow GICv3 compilation with older binutils
GICv3 introduces new system registers accessible with the full msr/mrs syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent binutils understand the new syntax. This patch introduces msr_s/mrs_s assembly macros which generate the equivalent instructions above and converts the existing GICv3 code (both drivers/irqchip/ and arch/arm64/kernel/). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Olof Johansson <olof@lixom.net> Tested-by: Olof Johansson <olof@lixom.net> Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> (cherry picked from commit 72c5839515260dce966cd24f54436e6583288e6c) Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm64/kernel/head.S')
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 5a24c05f08b6..650ec9ea42fd 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -180,12 +180,12 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
cmp x0, #1
b.ne 3f
- mrs x0, ICC_SRE_EL2
+ mrs_s x0, ICC_SRE_EL2
orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
- msr ICC_SRE_EL2, x0
+ msr_s ICC_SRE_EL2, x0
isb // Make sure SRE is now set
- msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
+ msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults