path: root/arch/arm/mach-keystone
diff options
authorRussell King <rmk+kernel@arm.linux.org.uk>2015-04-04 20:09:46 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-06-01 23:48:19 +0100
commitb2c3e38a54714e917c9e8675ff5812dca1c0f39d (patch)
tree0d5e9747b2c73ccd4c961c8d6a50841b52cf11fd /arch/arm/mach-keystone
parent1221ed10f2a56ecdd8ff75f436f52aca5ba0f1d3 (diff)
ARM: redo TTBR setup code for LPAE
Re-engineer the LPAE TTBR setup code. Rather than passing some shifted address in order to fit in a CPU register, pass either a full physical address (in the case of r4, r5 for TTBR0) or a PFN (for TTBR1). This removes the ARCH_PGD_SHIFT hack, and the last dangerous user of cpu_set_ttbr() in the secondary CPU startup code path (which was there to re-set TTBR1 to the appropriate high physical address space on Keystone2.) Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-keystone')
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
index 5f46a7cf907b..4bbb18463bfd 100644
--- a/arch/arm/mach-keystone/platsmp.c
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -39,19 +39,6 @@ static int keystone_smp_boot_secondary(unsigned int cpu,
return error;
-static void __cpuinit keystone_smp_secondary_initmem(unsigned int cpu)
- pgd_t *pgd0 = pgd_offset_k(0);
- cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
- local_flush_tlb_all();
-static inline void __cpuinit keystone_smp_secondary_initmem(unsigned int cpu)
struct smp_operations keystone_smp_ops __initdata = {
.smp_boot_secondary = keystone_smp_boot_secondary,
- .smp_secondary_init = keystone_smp_secondary_initmem,