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authorInderpal Singh <inderpal.singh@linaro.org>2013-04-29 17:01:47 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-05-19 11:38:41 -0700
commit56b02ed3e6e99fcf97a4eef0fccba2bb70e44975 (patch)
tree8aae6a1ca39c49e2125ced0426e53fb5adb60d53 /arch/arm/mach-exynos/include/mach/regs-pmu.h
parenta7a715466b67d5c0c1c29f7785838393a45c3700 (diff)
ARM: EXYNOS5: Fix kernel dump in AFTR idle mode
commit 088584618836b159947bc4ab5011a5cf1f081a62 upstream. The kernel crashes while resuming from AFTR idle mode. It happens because L2 cache was not going into retention state. This patch configures the USE_RETENTION bit of ARM_L2_OPTION register so that it does not depend on MANUAL_L2RSTDISABLE_CONTROL of ARM_COMMON_OPTION register for L2RSTDISABLE signal. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Tested-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-pmu.h')
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 3f30aa1ae354..57344b7e98ce 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -344,6 +344,7 @@
#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
+#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)