diff options
| author | Robert Tivy <rtivy@ti.com> | 2013-01-10 16:23:23 -0800 |
|---|---|---|
| committer | Sekhar Nori <nsekhar@ti.com> | 2013-01-22 17:42:59 +0530 |
| commit | af47e6bb8866ad57cfcfeceecf799edc3a658660 (patch) | |
| tree | f91c474cdd8988e9a959b66f0d6c22032f2ffe71 /arch/arm/mach-davinci/clock.h | |
| parent | 35031f9df569913ac0c46b03c8033fc1deed749d (diff) | |
ARM: davinci: psc: introduce reset API
Introduce an IP reset API for use on DaVinci SoC.
There is no existing "reset" framework support for SoC devices.
The remoteproc driver needs explicit control of the DSP's reset line.
To support this, a new DaVinci specific API is added.
This private API will disappear with DT migration. Some discussion
regarding a proposed DT "reset" binding is here:
https://patchwork.kernel.org/patch/1635051/
Modify davinci_clk_init() to set clk "reset" function for clocks
that indicate PSC_LRST support. Also fix indentation issue with
function opening curly brace.
Signed-off-by: Robert Tivy <rtivy@ti.com>
[nsekhar@ti.com: rename davinci_psc_config_reset() to davinci_psc_reset()]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/clock.h')
| -rw-r--r-- | arch/arm/mach-davinci/clock.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 46f0f1bf1a4c..8694b395fc92 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -103,6 +103,7 @@ struct clk { unsigned long (*recalc) (struct clk *); int (*set_rate) (struct clk *clk, unsigned long rate); int (*round_rate) (struct clk *clk, unsigned long rate); + int (*reset) (struct clk *clk, bool reset); }; /* Clock flags: SoC-specific flags start at BIT(16) */ @@ -112,6 +113,7 @@ struct clk { #define PRE_PLL BIT(4) /* source is before PLL mult/div */ #define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ #define PSC_FORCE BIT(6) /* Force module state transtition */ +#define PSC_LRST BIT(8) /* Use local reset on enable/disable */ #define CLK(dev, con, ck) \ { \ @@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); int davinci_set_refclk_rate(unsigned long rate); int davinci_simple_set_rate(struct clk *clk, unsigned long rate); +int davinci_clk_reset(struct clk *clk, bool reset); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); |