diff options
| author | Andrew Victor <linux@maxim.org.za> | 2008-10-13 20:28:13 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-12-01 17:18:08 +0000 |
| commit | 6781002bec5237ee8ac1e1daeb0ba976e780a884 (patch) | |
| tree | 4072b3d6f46c3f48db973aefec5e21cc724f7d9a /arch/arm/mach-at91/sam9_smc.c | |
| parent | 37efe6427dd50e889473fb3c7fcec02dbbd098eb (diff) | |
[ARM] 5287/2: [AT91] Configuration of Static Memory Controller
Add a structure 'sam9_smc_config' and function sam9_smc_configure() to
allow the board-specific files to specify the configuration of the
Static Memory Controller per chip-select. This allows the board file
to specify timings for NAND flash, NOR flash or other external
peripherals.
This functionality can be used for all the SAM9 and CAP9 processors.
(the AT91RM9200 has a different memory-controller)
This patch is based on similar code in the AVR32 architecture.
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/sam9_smc.c')
| -rw-r--r-- | arch/arm/mach-at91/sam9_smc.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c new file mode 100644 index 000000000000..5eab6aa621d0 --- /dev/null +++ b/arch/arm/mach-at91/sam9_smc.c @@ -0,0 +1,47 @@ +/* + * linux/arch/arm/mach-at91/sam9_smc.c + * + * Copyright (C) 2008 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/io.h> + +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" + +void __init sam9_smc_configure(int cs, struct sam9_smc_config* config) +{ + /* Setup register */ + at91_sys_write(AT91_SMC_SETUP(cs), + AT91_SMC_NWESETUP_(config->nwe_setup) + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) + | AT91_SMC_NRDSETUP_(config->nrd_setup) + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup) + ); + + /* Pulse register */ + at91_sys_write(AT91_SMC_PULSE(cs), + AT91_SMC_NWEPULSE_(config->nwe_pulse) + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) + | AT91_SMC_NRDPULSE_(config->nrd_pulse) + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse) + ); + + /* Cycle register */ + at91_sys_write(AT91_SMC_CYCLE(cs), + AT91_SMC_NWECYCLE_(config->write_cycle) + | AT91_SMC_NRDCYCLE_(config->read_cycle) + ); + + /* Mode register */ + at91_sys_write(AT91_SMC_MODE(cs), + config->mode + | AT91_SMC_TDF_(config->tdf_cycles) + ); +} |