diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2006-01-12 16:53:51 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-12 16:53:51 +0000 |
| commit | 90303b102353302e84758f245906368907e6a23b (patch) | |
| tree | 3e417666985ee5875c2d3435518de2c4bdc9b88d /arch/arm/lib/csumpartialcopyuser.S | |
| parent | ece5f7b3c4fde70a1ae4add7372ebca5c90bc34d (diff) | |
[ARM] 3256/1: Make the function-returning ldm's use sp as the base register
Patch from Catalin Marinas
If the low interrupt latency mode is enabled for the CPU (from ARMv6
onwards), the ldm/stm instructions are no longer atomic. An ldm instruction
restoring the sp and pc registers can be interrupted immediately after sp
was updated but before the pc. If this happens, the CPU restores the base
register to the value before the ldm instruction but if the base register
is not sp, the interrupt routine will corrupt the stack and the restarted
ldm instruction will load garbage.
Note that future ARM cores might always run in the low interrupt latency
mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/lib/csumpartialcopyuser.S')
| -rw-r--r-- | arch/arm/lib/csumpartialcopyuser.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index 333bca292de9..c3b93e22ea25 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -18,11 +18,13 @@ .text .macro save_regs + mov ip, sp stmfd sp!, {r1 - r2, r4 - r8, fp, ip, lr, pc} + sub fp, ip, #4 .endm - .macro load_regs,flags - ldm\flags fp, {r1, r2, r4-r8, fp, sp, pc} + .macro load_regs + ldmfd sp, {r1, r2, r4-r8, fp, sp, pc} .endm .macro load1b, reg1 @@ -100,5 +102,5 @@ 6002: teq r2, r1 strneb r0, [r1], #1 bne 6002b - load_regs ea + load_regs .previous |