path: root/arch/arm/lib/csumpartialcopygeneric.S
diff options
authorCatalin Marinas <catalin.marinas@arm.com>2006-01-12 16:53:51 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-01-12 16:53:51 +0000
commit90303b102353302e84758f245906368907e6a23b (patch)
tree3e417666985ee5875c2d3435518de2c4bdc9b88d /arch/arm/lib/csumpartialcopygeneric.S
parentece5f7b3c4fde70a1ae4add7372ebca5c90bc34d (diff)
[ARM] 3256/1: Make the function-returning ldm's use sp as the base register
Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/lib/csumpartialcopygeneric.S')
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index 4a4609c19095..c50e8f5285d1 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -23,7 +23,7 @@ len .req r2
sum .req r3
.Lzero: mov r0, sum
- load_regs ea
+ load_regs
* Align an unaligned destination pointer. We know that
@@ -87,9 +87,7 @@ sum .req r3
b .Ldone
- mov ip, sp
- sub fp, ip, #4
cmp len, #8 @ Ensure that we have at least
blo .Lless8 @ 8 bytes to copy.
@@ -163,7 +161,7 @@ FN_ENTRY
ldr sum, [sp, #0] @ dst
tst sum, #1
movne r0, r0, ror #8
- load_regs ea
+ load_regs
adc sum, sum, #0 @ include C from dst alignment