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authorWill Deacon <will.deacon@arm.com>2012-07-29 12:36:28 +0100
committerWill Deacon <will.deacon@arm.com>2012-08-23 11:35:52 +0100
commit6dbc00297095122ea89e016ce6affad0b7c0ddac (patch)
treef3c01a92818dd1a8e9cf9cd9a52cae8229332c55 /arch/arm/include/asm/perf_event.h
parent04236f9fe07462849215c67cae6147661368bfad (diff)
downloadlinux-linaro-stable-6dbc00297095122ea89e016ce6affad0b7c0ddac.tar.gz
ARM: perf: prepare for moving CPU PMU code into separate file
The CPU PMU code is tightly coupled with generic ARM PMU handling code. This makes it cumbersome when trying to add support for other ARM PMUs (e.g. interconnect, L2 cache controller, bus) as the generic parts of the code are not readily reusable. This patch cleans up perf_event.c so that reusable code is exposed via header files to other potential PMU drivers. The CPU code is consistently named to identify it as such and also to prepare for moving it into a separate file. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include/asm/perf_event.h')
-rw-r--r--arch/arm/include/asm/perf_event.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948d8143..625cd621a436 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
#ifndef __ARM_PERF_EVENT_H__
#define __ARM_PERF_EVENT_H__
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS 32
+
+#define HW_OP_UNSUPPORTED 0xFFFF
+#define C(_x) PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED 0xFFFF
#endif /* __ARM_PERF_EVENT_H__ */