diff options
| author | Andrew Lunn <andrew@lunn.ch> | 2014-02-22 20:14:52 +0100 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-22 20:43:49 +0000 |
| commit | 4b8f7a11c9fb680895e5079788653a59d6bdde16 (patch) | |
| tree | d20f78bd55eb043f8f9e1be5e702301263b73079 /arch/arm/include/asm/hardware | |
| parent | 3c317d00ba4a9489c161857a574432c61fde4a2a (diff) | |
ARM: MM: Add DT binding for Feroceon L2 cache
Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/include/asm/hardware')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-feroceon-l2.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 8edd330aabf6..12e1588dc4f1 100644 --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + |